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SystemVerilog Enhanced Data Types and Expressions

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swaroop
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12 views

SystemVerilog Enhanced Data Types and Expressions

Uploaded by

swaroop
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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SystemVerilog: Enhanced

Data Types and


Expressions
.

by Swaroop D
4MH21EC104
Constants
• In SystemVerilog, parameters can be declared at the $root level so they can
be global. This approach can replace many Verilog macros that were just
being used as constants. 

• You can use a typedef to replace those clunky macros. The next choice is a
parameter. A Verilog parameter was loosely typed and was limited in scope
to a single module.

• SystemVerilog also supports the const modifier that allows you to make a
variable that can be initialized in the declaration but not written by
procedural code.
EXAMPLE : Declaring a const variable

intial begin
const byte colon = “:”;
…
end
Strings
• The SystemVerilog string type holds variable-length strings. An individual
character is of type byte. The elements of a string of length N are
numbered 0 to N-1.

• Note that, unlike C, there is no null character at the end of a string, and
any attempt to use the character “\0” is ignored.

• Strings use dynamic memory allocation, so you do not have to worry about
running out of space to store the string
Example Program
string s;
initial begin
s="SystemVerilog";
$display(s.getc(0)); // Display: 83 (‘S’)
$display (s.toupper()); //
Display:SYSTEMVERILOG

s ={s, "3.1b“}; //
"SystemVerilog3.1b“
s.putc(s.len (-1, "a"); // change b-> a
$display(s.substr(2, 5));// Display: stem
// Create temporary string, note format
my_log($psprintf("%s %5d", s, 42));
end

task my_log(string message):


// Print a message to a log
$display ("@%0d: %s", $time, message);
endtask
Expressions
A prime source for unexpected behavior in Verilog has
been the width of expressions. Example 2-40 adds 1 + 1
using four different styles. Addition A uses two 1-bit
. variables, so with this precision 1+1=0. Addition B uses 8-
bit precision because there is an 8-bit variable on the right
side of an assignment. In this case, 1+1=2. Addition c
uses a dummy constant to force SystemVerilog to use 2-bit
precision. Lastly, in addition D, the first value is cast to be
a 2- bit value with the cast operator, so 1+1=2.

Example: Expression width depends on context :

bit [7:0] b8;


bit one = 1’ b1 // Single bit
$displayb (one + one); //A: 1 + 1 = 0

b * 8 = one + one // B: 1+1=2


$displayb (b8);

$displayb (one one + 2'b0); // C: 1+1= 2 with constant

$displayb (2' * (one) + one); // D: 1+12 with cast

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