RISC and CISC, Parallel Processing
RISC and CISC, Parallel Processing
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RISC (Reduced Instruction Set Computer)
The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s and early 80s.
RISC stands for Reduced Instruction Set Computer. To execute each instruction, if there is separate electronic
circuitry in the control unit, which produces all the necessary signals, this approach of the design of the control
section of the processor is called RISC design. It is also called hard-wired approach.
Examples of RISC processors: x IBM RS6000, MC88100. x DEC’s Alpha 21064, 21164 and 21264 processors
Features of RISC Processors: The standard features of RISC processors are listed below:
RISC processors use a small and limited number of instructions.
RISC processors consume less power and are having high performance.
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Reduced Instruction Set Computer (RISC)
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CISC (Complex Instruction Set Computer)
CISC stands for Complex Instruction Set Computer. If the control unit contains a number of
microelectronic circuitry to generate a set of control signals and each micro-circuitry is activated by a
microcode, this design approach is called CISC design.
Examples of CISC processors are: x Intel 386, 486, Pentium, Pentium Pro, Pentium II, Pentium III x
Motorola’s 68000, 68020, 68040, etc.
Features of CISC Processors: The standard features of CISC processors are listed below:
CISC chips have a large amount of different and complex instructions.
CISC machines generally make use of complex addressing modes.
Different machine programs can be executed on CISC machine.
CISC machines uses micro-program control unit.
CISC processors are having limited number of register
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CISC Processors Architecture
The CISC architecture helps reduce program code by embedding multiple operations on each program
instruction, which makes the CISC processor more complex.
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Complex Instruction Set Computer (CISC) Characteristics
Some instructions that perform specialized tasks and are used infrequently
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Simple Difference 1
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Simple Difference 2
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Difference between the RISC and CISC
RISC CISC
It is a Reduced Instruction Set Computer. It is a Complex Instruction Set Computer.
It emphasizes on software to optimize the instruction set. It emphasizes on hardware to optimize the instruction
set.
It is a hard wired unit of programming in the RISC Processor. Microprogramming unit in CISC Processor.
It requires multiple register sets to store the instruction. It requires a single register set to store the instruction.
RISC has simple decoding of instruction. CISC has complex decoding of instruction.
Uses of the pipeline are simple in RISC. Uses of the pipeline are difficult in CISC.
It uses a limited number of instruction that requires less time to execute It uses a large number of instruction that requires
the instructions. more time to execute the instructions.
It uses LOAD and STORE that are independent instructions in the It uses LOAD and STORE instruction in the memory-
register-to-register a program's interaction. to-memory interaction of a program.
RISC has more transistors on memory registers. CISC has transistors to store complex instructions.
The execution time of RISC is very short. The execution time of CISC is longer.
RISC architecture can be used with high-end applications like CISC architecture can be used with low-end applications like
telecommunication, image processing, video processing, etc. home automation, security system, etc.
The program written for RISC architecture needs to take more space in Program written for CISC architecture tends to take less 10
memory. space in memory.
Parallel Processing
Parallel processing is a method in computing of running two or more processor (CPUs) to handle
separate parts of an overall task. Breaking up different parts of a task among multiple processors will
help reduce the amount of time to run a program. Any system that has more than one CPU can perform
parallel processing, as well as multi-core processors which are commonly found on computers today.
Multi-core processors are IC chips that contain two or more processors for better performance, reduced
power consumption and more efficient processing of multiple tasks.
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How Does Parallel Processing Work?
In general, parallel processing refers to dividing a task between at least two microprocessors.
The idea is very straightforward: a computer scientist uses specialized software created for the task to break down
a complex problem into its component elements. Then, they designate a specific processor for each part. To
complete the entire computing problem, each processor completes its portion. The software reassembles the data
to solve the complex initial challenge.
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Types of Parallel Processing
Single Instruction, Single Data (SISD)
In the type of computing called Single Instruction, Single Data (SISD), a single processor is responsible
for simultaneously managing a single algorithm as a single data source.
Multiple Instruction, Single Data (MISD)
Multiple processors are standard in computers that use the Multiple Instruction, Single Data (MISD)
instruction set. While using several algorithms, all processors share the same input data.
Single Instruction, Multiple Data (SIMD)
Computers that use the Single Instruction, Multiple Data (SIMD) architecture have multiple processors
that carry out identical instructions.
Multiple Instruction, Multiple Data (MIMD)
Multiple Instruction, Multiple Data, or MIMD, computers are characterized by the presence of multiple
processors, each capable of independently accepting its instruction stream.
Single Program, Multiple Data (SPMD)
SPMD systems, which stand for Single Program, Multiple Data, are a subset of MIMD. Although an
SPMD computer is constructed similarly to a MIMD, each of its processors is responsible for carrying
out the same instructions.
Massively Parallel Processing (MPP)
A storage structure called Massively Parallel Processing (MPP) is made to manage the coordinated
execution of program operations by numerous processors.
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Parallel Processing Examples
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Question Practice
a. Time delay
b. Semantic gap
c. Cost
d. All of the above
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2. Which of these architectures is power efficient?
a. IANA
b. ISA
c. CISC
d. RISC
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3. Pipe-lining is the special feature of ____________.
a. IANA
b. ISA
c. CISC
d. RISC
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4. In CISC architecture most of the complex
instructions are stored in _____.
a) Register
b) Diodes
c) Capacitor
d) Transistors
Answer: Transistors
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5. The cost of a parallel processing is primarily
determined by :
a) time complexity
b) switching complexity
c) circuit complexity
d) none of the above
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6. Parallel processing may occur
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Thank
You
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