Base Narrowing

• The effective base width Wb is essentially independent of the bias

voltages applied to the collector and emitter junctions. This assumption
is not always valid;
• the p-n-p transistor of Fig. is affected by the reverse bias applied to the
collector. If the base region is lightly doped, the depletion region at the
reverse-biased collector junction can extend significantly into the n-type
base region.
• As the collector voltage is increased, the space charge layer takes up
more of the metallurgical width of the base Lb, and as a result, the
effective base width Wb is decreased.
• This effect is variously called base narrowing, base-width
modulation, and the Early effect after J. M. Early, who first
interpreted it.
• The effects of base narrowing are apparent in the collector characteristics
for the common-emitter configuration (Fig. b).
• The decrease in Wb causes β to increase.
• As a result, the collector current IC increases with collector voltage
rather than staying constant as predicted from the simple treatment.
• The slope introduced by the Early effect is almost linear with IC,
and the common-emitter characteristics extrapolate to an
intersection with the voltage axis at VA, called the Early voltage.
• For the p-n-p- device of Fig. - we can approximate the length l of
the collector junction depletion region in the n material with V0
replaced by V0 - VCB and VCB taken to be large and negative:

• If the reverse bias on the collector junction is increased far enough,

it is possible to decrease Wb to the extent that the collector
depletion region essentially fills the entire base.
• In this punch-through condition holes are swept directly from
the emitter region to the collector, and transistor action is lost.
• Punch-through is a breakdown effect that is generally
avoided in circuit design.
• In most cases, however, avalanche breakdown of the collector
junction occurs before punch-through is reached.
• In devices with graded base doping, base narrowing is of less
importance.
• For example, if the donor concentration in the base region of a p-n-
p increases with position from the collector to the emitter, the
intrusion of the collector space charge region into the base
becomes less important with increased bias as more donors are
available to accommodate the space charge.
Avalanche Breakdown
• Before punch-through occurs in most transistors, avalanche
multiplication at the collector junction becomes important.
• As Fig. indicates, the collector current increases sharply at a well-
defined breakdown voltage BVCBO for the common-base configuration.
• For the common-emitter case, however, there is a strong influence of
carrier multiplication over a fairly broad range of collector voltage.
• Furthermore, the breakdown voltage in the common-emitter case BVCEO
is significantly smaller than BVCBO.
• We can understand these effects by considering breakdown for the
condition IE = 0 in the common-base case and for IB = 0 in the
common-emitter case. These conditions are implied by the O in the
subscripts of BVCEO and BVCBO.
• In each case the terminal current IC is the current entering the collector
depletion region multiplied by the factor M.
• Including multiplication due to impact ionization, Eq. becomes
• For the limiting common-base case of IE = 0 (the lowest curve in Fig.), IC
is simply MICO, and the breakdown voltage is well defined, as in an
isolated junction.
• The term BVCBO signifies the collector junction breakdown voltage in
common-base with the emitter open.
• COMMON EMITTER CASE
• In the common emitter case, the situation is somewhat more
complicated.
• Setting IB = 0, and therefore, IC = IE in Eq. we have

• In this case the collector current increases indefinitely, when MαN

approaches unity.
• By contrast, M must approach infinity in the common-base case before
BVCBO is reached.
• Since α N is close to unity in most transistors, M need be only slightly
larger than unity for Eq. to approach breakdown.
• Avalanche multiplication thus dominates the current in a common-
emitter transistor well below the breakdown voltage of the isolated
collector junction.
• The sustaining voltage for avalanching in the common-emitter case
Process flow for double polysilicon, self aligned n-p-n BJT:

a) n+ buried layer formation;

(b) n epitaxy followed by LOCOS(location

the sub-collectors) isolation;

c) base emitter window definition and

(optional) masked “sinker” implant
(P) into collector contact region;
• (d) intrinsic base implant
using self-aligned oxide
sidewall spacers;

• e) self-aligned formation
of n+ emitter, as well as
n+ collector
• contact.
• The first transistor invented by Bardeen and Brattain in 1947 was the point contact
transistor.
• In this device two sharp metal wires, or “cat’s whiskers,” formed an “emitter” of
carriers and a “collector” of carriers.
• These wires were simply pressed onto a slab of Ge which provided a “base” or
mechanical support, through which the injected carriers flowed.
• This basic invention rapidly led to the BJT, in which charge injection and collection was
achieved using two p-n junctions in proximity to each other.
• The p-n junctions in BJTs can be formed in a variety of ways using thermal diffusion,
but modern devices are generally made using ion implantation.
• Let us review a simplified version of how to make a double polysilicon, self-aligned
n-p-n Si BJT.
• This is the most commonly used, state-of-the-art technique for making BJTs for use in
an IC.
• Use of n-p-n transistors is more popular than p-n-p devices because of the higher
mobility of electrons compared with holes.
• The process steps are shown in cross-sectional view in Fig. 7–5. A p-type Si substrate is
oxidized, windows are defined using photolithography and etched in the oxide.
• Using the photoresist and oxide as an implant mask, a donor with very small diffusivity
in Si, such as As or Sb, is implanted into the open window to form a highly conductive
n+ layer.
• Subsequently, the photoresist and the oxide are removed, and a lightly doped n-type epitaxial layer is
grown.
• During this high temperature growth, the implanted n+ layer diffuses only slightly toward the surface
and becomes a conductive buried collector (also called a sub-collector).
• The n+ sub-collector layer guarantees a low collector series resistance when it is connected
subsequently to the collector ohmic contact, sometimes through the use of an optional, masked deep n+
“sinker” implant or diffusion only in the collector contact region (Fig. 7–5c).
• The lightly doped n-type collector region above the n+ sub-collector in the part of the BJT where the base
and emitter are formed ensures a high base-collector reverse breakdown voltage.
• (It turns out that wherever the sub-collector is formed, and subsequently the epitaxial layer is grown on
top, there is a notch or step in the substrate surface. This notch is not explicitly shown in Fig. 7–5a.
• This notch is very useful as a marker of the location of the sub-collectors because, subsequently, we
have to align the LOCOS isolation mask with respect to the sub-collector.)
• For integrated circuits involving not just discrete BJTs, but many interconnected transistors, there are
issues involving electrical isolation of adjacent BJTs in order to ensure that there is no electrical cross-talk
between them.
• As described in Section 6.4.1, such an isolation can be achieved by LOCOS to form field or isolation
oxides after a B channel stops implant (Fig. 7–5b).
• Another isolation scheme that is particularly well suited for high-density bipolar circuits involves the
formation of shallow trenches by reactive ion etching (RIE), backfilled with oxide and polysilicon (Section
9.3.1).
• In this process a nitride layer is patterned and used as an etch mask for an anisotropic etch of the silicon
to form the trench.
• Using RIE, a narrow trench about 1 mm deep can be formed with very straight sidewalls.
• Oxidation inside the trench forms an insulating layer, and the trench is then filled with oxide by low-
pressure chemical vapor deposition (LPCVD).
• A polysilicon layer is deposited by LPCVD, and doped heavily p+ with B either during
deposition or subsequently by ion implantation.
• An oxide layer is deposited next by LPCVD. Using photolithography with the
base/emitter mask, a window is etched in the polysilicon/oxide stack by RIE (Fig. 7–5c).
• A heavily doped “extrinsic” p+ base is formed by diffusion of B from the doped
polysilicon layer into the substrate in order to provide a low-resistance, high-speed
base ohmic contact.
• An oxide layer is then deposited by LPCVD, which has the effect of closing up the base
window that was etched previously, and B is implanted into this window (Fig. 7–5d).
• This base implant forms a more lightly p doped “intrinsic” base through which most of
the current flows from the emitter to the collector.
• The more heavily doped extrinsic base forms a collar around the intrinsic base, and
serves to reduce the base series resistance.
• It is critical that the base be enclosed well within the collector because otherwise it
would be shorted to the p substrate.
• Finally, another LPCVD oxide layer is deposited to close up the base window further,
and the oxide is etched all the way to the Si substrate by RIE, leaving oxide spacers on
the sidewalls. Heavily n+ doped (typically with As) polysilicon is then deposited on the
substrate, patterned and etched, forming polysilicon emitter (polyemitter) and collector
contacts, as shown in Fig. 7–5e. (The use of two LPCVD polysilicon layers explains why
this process is referred to as the double-polysilicon process.)
• Arsenic from the polysilicon is diffused into the substrate to form the n+ emitter region
nested within the base in a self-aligned manner, as well as the n+ collector contact.
• Self-alignment refers to the fact that a separate lithography step is not required to form
the n+ emitter region.
• We cleverly made use of the oxide sidewall spacers to ensure that the n+ emitter
region lies within the intrinsic p-type base.
• This is critical because otherwise the emitter gets shorted to the collector; we also
want a gap between the n+ emitter and the p+ extrinsic base, because otherwise the
emitter–base junction capacitance becomes too high.
• In the vertical direction, the difference between the emitter–base junction and the
base–collector junction determines the base width.
• This is made very narrow in high gain, high speed BJTs.
• Finally, an oxide layer is deposited by CVD, windows are etched in it corresponding to
the emitter (E), base (B), and collector (C) contacts, and a suitable contact metal such
as Al is sputter deposited to form the ohmic contacts.
• The Al is patterned photolithographically using the interconnect mask, and etched
using RIE. The many ICs that are made simultaneously on the wafer are then separated
into individual dies by sawing, mounted on suitable packages, and the various contacts
are wire bonded to the external leads of the package.