11-1 Peripheral Devices

The text discusses the input-output organization of computer systems, including

the role of keyboards, peripheral devices, and interfaces in transferring data
between internal storage and external devices.

11-2 Input-Output Interface

2024
 Key concepts

• central processing unit

• Direct memory access
• record separator
• chip select
• carriage return
• file separator
• horizontal tabulation
• high speed
• cathode ray tube
• Peripheral Devices
• computer memory
 Abstract

The most familiar means of entering information into a computer is through a typewriter-like keyboard
that allows a person to enter forming operations at very high speed. When input information is
transferred to the processor via a slow keyboard, the processor will be idle most of the time while waiting
for the information to arrive. To use a computer efficiently, a
 Highlights

• The limitations of the text are that it does not provide a comprehensive overview of all input-output
devices and interfaces, and that it does not discuss the limitations of different modes of transfer.
• The programmed I/O method is time-consuming and keeps the processor busy needlessly.
• The future work suggested by the text is to explore new modes of transfer and to improve the
efficiency and effectiveness of data transfer between internal storage and external devices.
• There is no mention of future work in the text.
• The practical applications of the text are in the design and implementation of computer systems,
particularly in the development of input-output interfaces and peripheral devices.
• The use of interrupt facilities can have practical applications in improving data transfer efficiency in
computer systems.
 Peripheral Devices

Peripheral devices are electromechanical and electromagnetic devices that are connected to a computer
and are under its direct control.
They are used to enter information into a computer and to transmit results in a meaningful form.
Examples of peripherals include keyboards, display units, printers, magnetic disks, and tapes.
These devices are designed to read information into or out of the memory unit upon command from the
CPU and are considered part of the total computer system.
Video monitors are a type of peripheral that consists of a keyboard as the input device and a display unit
as the output device.
They use a cathode ray tube (CRT) to produce a pattern on the screen, and a cursor that marks the
position on the screen where the next character will be inserted.
Printers provide a permanent record on paper of computer output data or text.
There are three basic types of character printers: daisywheel, dot matrix, and laser printers.
Magnetic tapes and disks are used for storing files of data and programs, and are discussed further in
Section 12-1.
Input/Output Interface And Asynchronous Data
Transfer
The input/output (I/O) interface is a crucial component in computer systems, enabling communication
between the central processing unit (CPU) and external devices.
The interface operates in different modes, including status, data output, and data input.
The CPU uses control commands to initiate data transfer, monitor the status of the peripheral, and detect
errors.
There are three ways to communicate with memory and I/O: using separate buses, one common bus with
separate control lines, or one common bus with common control lines.
The isolated I/O method uses separate read and write lines for memory and I/O, while the memory-
mapped I/O method treats interface registers as part of the memory system.
An I/O interface unit consists of data registers, a control register, a status register, bus buffers, and
timing and control circuits.
The interface communicates with the CPU through the data bus, and the chip select and register select
inputs determine the address assigned to the interface.
Asynchronous data transfer occurs between two independent units, such as the CPU and an I/O interface,
 Data Transfer Methods

Data transfer between units can occur through two methods: strobe transfer and handshaking.
In strobe transfer, the source unit places data on the bus and activates a strobe pulse to inform the
destination unit.
The destination unit then receives the data and the strobe pulse is disabled.
The source unit removes the data from the bus after a brief period.
This method has a disadvantage in that the source unit has no way of knowing if the destination unit has
received the data.
In handshaking, a second control signal is introduced to provide a reply to the unit that initiates the
transfer.
One control line is used by the source unit to inform the destination unit of valid data, and the other
control line is used by the destination unit to inform the source unit that it can accept data.
The sequence of control depends on the unit that initiates the transfer.
Handshaking provides a high degree of flexibility and reliability, and errors can be detected through a
timeout mechanism.
 Asynchronous Communication Interface

The asynchronous communication interface is a chip that communicates with the CPU through the chip
select and read and write control lines.
The interface has two registers that are write-only and two that are read-only.
The register selected is determined by the register select (RS) value and the read (RD) and write (WR)
status.
The interface is initialized by the CPU by sending a byte to the control register, which defines parameters
such as baud rate, character bits, parity, and stop bits.
The interface has two flags in the status register: one indicates whether the transmitter register is
empty, and the other indicates whether the receiver register is full.
The transmitter portion of the interface operates by checking the flag, transferring a character to the
transmitter register, and then transmitting the character one bit at a time at the specified baud rate.
The receiver portion of the interface operates similarly, receiving a character and transferring it to the
receiver register.
The interface checks for errors during transmission, including parity error, framing error, and overrun
 FIFO Buffer

A FIFO (first-in, first-out) buffer is a memory unit that stores information in the order it is received and
outputs it in the same order.
It has separate input and output terminals and can accept data at one rate and deliver it at another rate.
The FIFO buffer is useful in asynchronous data transfer applications where data are transferred at
different rates.
A typical 4x4 FIFO buffer consists of four 4-bit registers and a control register with flip-flops.
The control register directs the movement of data through the registers.
Data are inserted into the buffer when the input ready signal is enabled, and they are output when the
output ready control line is enabled.
 Modes Of Transfer

Data transfer between the central computer and I/O devices can be handled in three modes:
programmed I/O, interrupt-initiated I/O, and direct memory access (DMA).
Programmed I/O involves the CPU initiating each data transfer and monitoring the peripheral.
Interrupt-initiated I/O uses an interrupt facility to inform the CPU when the peripheral is ready for data
transfer.
DMA transfers data directly into and out of the memory unit through the memory bus, without involving
the CPU.
 Data Transfer And Interrupts

Data transfer from an I/O device to memory involves several CPU instructions.
The CPU first reads data from the device into its register and then stores it in memory.
This process requires checking if data is available and counting the number of words transferred.
The device sends data one byte at a time, using a handshaking procedure to ensure proper timing.
The CPU checks a flag in the status register to know when data is ready, reads the data, and then clears
the flag to allow the next byte transfer.
This programmed I/O method is inefficient because the CPU spends a lot of time checking the flag
instead of performing other tasks.
An alternative is using interrupts, where the device signals the CPU when it is ready to transfer data.
The CPU temporarily stops its current task to handle the data transfer and then resumes its previous
task.
Interrupts can be vectored or nonvectored, determining how the CPU finds the service routine to handle
the interrupt.
Priority interrupts manage multiple devices requesting service simultaneously by assigning priority
 Interrupt Handling

In a daisy-chaining scheme, devices are connected in a way that the device closest to the CPU has the
highest priority.
Each device has an internal logic that includes an RF flip-flop, which is set when the device wants to
interrupt the CPU.
The output of the RF flip-flop goes through an open-collector inverter, providing the wired logic for the
common interrupt line.
In the parallel priority interrupt method, a register is used to establish priority according to the position of
the bits in the register.
A mask register can be used to control the status of each interrupt request, allowing higher-priority
devices to interrupt the CPU while lower-priority devices are being serviced.
The priority logic for a system of four interrupt sources consists of an interrupt register, a mask register,
and a priority encoder.
The interrupt register is set by external conditions and cleared by program instructions.
The mask register has the same number of bits as the interrupt register and can be programmed to set