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Digital VLSIlayoutown

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34 views28 pages

Digital VLSIlayoutown

Uploaded by

ajithtech21600
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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AVM614-Digital VLSI

Circuits Lecture 3: Part II


Circuits & Layout

Dr.J.Sheeba Rani
Edited for Teaching
IIST
Detailed Mask Views
 Six masks
n well

– n-well
– Polysilicon
Polysilicon

– n+ diffusion
– p+ diffusion n+ Diffusion

– Contact p+ Diffusion

– Metal Contact

Metal

2 CMOS VLSI Design 4th Ed. 0: Introduction


How to build CMOS Circuits

 CMOS Inverter
 Pull Up network responsible for true VDD
output
 Pull down network responsible for
complementary output
A Y

GND
1: Circuits & Layout CMOS VLSI Design 4th Ed. 3
Layout
 Chips are specified with set of masks
 Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
 Feature size f = distance between source and drain
– Set by minimum width of polysilicon
 Feature size improves 30% every 3 years or so
 Normalize for feature size when describing design
rules
 Express rules in terms of λ = f/2
– E.g. λ = 0.3 μm in 0.6 μm process

0: Introduction CMOS VLSI Design 4th Ed. 4


Gate Layout
 Layout can be very time consuming
– Design gates to fit together nicely
– Build a library of standard cells
 Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts

1: Circuits & Layout CMOS VLSI Design 4th Ed. 5


Design Rules
 Two major approaches:
 – “Micron” rules: stated at micron resolution.
 – Lambda rules: simplified micron rules with limited
scaling attributes.
 Design rules represents a tolerance which insures
 very high probability of correct fabrication
 – scalable design rules: lambda parameter
 – absolute dimensions (micron rules)

1: Circuits & Layout CMOS VLSI Design 4th Ed. 6


CMOS 'λ' Design Rules
 The MOSIS stands for MOS Implementation Service
is the IC fabrication service available to universities
for layout, simulation, and test the completed
designs. The MOSIS rules are scalable λ rules.
 Lambda rules NOT used in commercial applications
– Lambda rules need to be very conservative and
thus waste space.

1: Circuits & Layout CMOS VLSI Design 4th Ed. 7


CMOS-Design Rules
 The CMOS design layouts are based on following
components :
(1) Substrates or Wells : These wells are p type for NMOS
devices and n type for PMOS devices.
(2) Diffusion regions : At these regions the transistors are
formed and also called as active layer. These are defined by
n+ for NMOS and p+ for PMOS transistors.
(3) Polysilicon layers : These are used to form the gate
electrodes of the transistors.
(4) Metal interconnects layers : These are used to form the
power supply and ground rails as well as input and output rails.
(5) Contact and Via layers : These are used to form the inter
layer connections.

1: Circuits & Layout CMOS VLSI Design 4th Ed. 8


What are design rules
 Length & Width of Transistor gate
  Separation between 2 wires on
same level
  Width of wires • Active area rules
Diffusion regions
  Contact pad for Vias • Polysilicon rules
  Cross section of Vias Gate regions/szing
  Size of Wells • Metal Rules
 … GnD/VDD
• Contact rules
Contact
sizing/separation etc.,
1: Circuits & Layout CMOS VLSI Design 4th Ed. 9
Simplified Design Rules
 Conservative rules to get you started

0: Introduction CMOS VLSI Design 4th Ed. 10


NMOS/PMOS Layout baed on
Lambda rules

1: Circuits & Layout CMOS VLSI Design 4th Ed. 11


Layout of Inverter
VDD

NWELL
P+
G -Contact cut
IN A
OUT
T
E
P Substrate not shown
N+
GND

1: Circuits & Layout CMOS VLSI Design 4th Ed. 12


N-MOS Geometry

1: Circuits & Layout CMOS VLSI Design 4th Ed. 13


Layout

1: Circuits & Layout CMOS VLSI Design 4th Ed. 14


Layout

Gate

Courtesy: https://www3.nd.edu/~kogge/courses/cse40462-VLSI-fa18/www/Public/Lectures/Design_
Rules.pdf

1: Circuits & Layout CMOS VLSI Design 4th Ed. 15


Layout

1: Circuits & Layout CMOS VLSI Design 4th Ed. 16


Layout

1: Circuits & Layout CMOS VLSI Design 4th Ed. 17


Inverter Layout-Views

1: Circuits & Layout CMOS VLSI Design 4th Ed. 18


Layout Example
Metal VDD Draw the equivalent Transisto
Schematic
Diffusion
P+
Gate VDD VDD

M2
M4

Metal Vin Vout Vout2

Diffusion M3
M1
N+
Contact
Cut
Metal GND
19 CMOS VLSI Design 4th Ed.
Transistor Width and length

1: Circuits & Layout CMOS VLSI Design 4th Ed. 20


Example: Inverter

1: Circuits & Layout CMOS VLSI Design 4th Ed. 22


Example: NAND3
 Horizontal N-diffusion and p-diffusion strips
 Vertical polysilicon gates
 Metal1 VDD rail at top
 Metal1 GND rail at bottom
 32  by 40 

1: Circuits & Layout CMOS VLSI Design 4th Ed. 23


Wiring Tracks
 A wiring track is the space required for a wire
– 4  width, 4  spacing from neighbor = 8  pitch
 Transistors also consume one wiring track

1: Circuits & Layout CMOS VLSI Design 4th Ed. 24


Well spacing
 Wells must surround transistors by 6 
– Implies 12  between opposite transistor flavors
– Leaves room for one wire track

1: Circuits & Layout CMOS VLSI Design 4th Ed. 25


Stick Diagrams
 Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
VDD VDD
A A B C
metal1
c poly
ndiff
pdiff
Y
Y contact

GND GND
INV NAND3

1: Circuits & Layout CMOS VLSI Design 4th Ed. 26


Area Estimation
 Estimate area by counting wiring tracks
– Multiply by 8 to express in 

40 

32 

1: Circuits & Layout CMOS VLSI Design 4th Ed. 27


Example: O3AI
 Sketch a stick diagram for O3AI and estimate area
–
Y  A  B  C D
A
VDD
A B C D B

6 tracks =
C D
Y
48  Y
D
A B C
GND
5 tracks =
40 

1: Circuits & Layout CMOS VLSI Design 4th Ed. 28


Stick Diagram-Compound Gate

1: Circuits & Layout CMOS VLSI Design 4th Ed. 29

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