MICROELECTRONICS-I

UNIT-I
B Tech ECE-B (Odd, 2023)
Dr Pavika Sharma BPIT 27-10-2023
 Introduction to Microelectronics

• Microelectronics is a subfield
of electronics. It is related to
the study and manufacture of
electronic
components/devices which
are very small (sub-micron
dimensions)
• These electronic
components/devices are
made from semiconductors.
• Microelectronics is based on
transistors (dominant device)
fabricated at sub-micron
dimensions as “integrated
circuits” or IC and measured
in micrometer (µm) scale.
Dr Pavika Sharma BPIT 27-10-2023
 Overview of Microelectronics Technology

Dr Pavika Sharma BPIT 27-10-2023

 Basic IC Fabrication Processes

Diffusion &
Photolithograp Ion Metallizatio
Oxidation
hy & Etching Implantatio n
n

Dr Pavika Sharma BPIT 27-10-2023

 (i) Oxidation: SiO2 film growth on Si-substrate

• SiO2 acts as an insulator, compared to Si and isolate devices in

the circuit.
• It works as a mask to prevent diffusion/ion implantation of
dopants into Si.

Before After Oxidation

Oxidation
Dr Pavika Sharma BPIT 27-10-2023
 (ii) Photolithography:

• Using light radiation (UV as it has

short wavelength) to expose a
coating of photoresist on the
surface of the wafer.

• A mask containing the required

geometric pattern for each layer
separates the light source from the
wafer, so that only the portions of
the photoresist not blocked by the
mask are exposed.

• Unwanted part is removed by the

process of etching.

• Positive and Negative photo-resists

are chosen as per requirement.
Dr Pavika Sharma BPIT 27-10-2023
 (iii) Diffusion & Ion Implantation:

Diffusion is carried out to dope the silicon substrate with

controlled amounts of a desired impurity.
Carried out in two steps:
1. Pre-deposition - the dopant is deposited onto wafer
surface.
2. Drive-in - heat treatment - the dopant is redistributed to
obtain the desired depth and concentration profile.

Ion Implantation is the process where vaporized ions of impurity

element are accelerated by an electric field and directed at silicon
substrate.
1. The atoms penetrate into surface, losing energy and finally
stopping at some depth in crystal structure determined by mass of
ion and acceleration voltage.
2. It can be accomplished at room temperature and is capable of
providing the exact doping density.

Dr Pavika Sharma BPIT 27-10-2023

 (iv) Metallization:

Metallization is the process to which uses various thin film deposition

technologies to form very fine patterns of conductive material.

Functions of conductive materials on wafer surface:

 Form certain components (e.g., gates) of IC devices
 Provide intra-connecting conduction paths between devices on
chip
 Connect the chip to external circuits

Dr Pavika Sharma BPIT 27-10-2023

Dr Pavika Sharma BPIT 27-10-2023
 Cleanroom Protocols & Safety Measures
Three-tiered approach:

Clean Factories Wafer Cleaning Gettering Treatment

Dr Pavika Sharma BPIT 27-10-2023

 HEPA: High Efficiency Particulate Air

1. HEPA filters and recirculation

for the air
2. Bunny Suits for workers
3. Filtration of Chemicals and
gases
4. Manufacturing Protocols

Dr Pavika Sharma BPIT 27-10-2023

 Chemical Cleaning:

Dr Pavika Sharma BPIT 27-10-2023

Dr Pavika Sharma BPIT 27-10-2023
 Gettering: process of removing device-degrading impurities from the
active circuit regions of the wafer. It is performed during crystal
growth, or in subsequent wafer fabrication steps, is an important
ingredient for enhancing the yield of VLSI manufacturing.

General Mechanism of Gettering,

1) the impurities to be gettered are released into solid solution from precipitate

form.

2) they undergo diffusion through the silicon

3) they are trapped by defects such as dislocations or precipitates in an area

away from device regions

Dr Pavika Sharma BPIT 27-10-2023
 Extrinsic Gettering

• it employs external means to create

the damage or stress in the
silicon lattice in such a way that
extended defects needed for
trapping impurities are formed.

Intrinsic Gettering

• involves impurity trapping sites

created by precipitating
supersaturated oxygen out of the
Dr Pavika Sharma BPIT silicon wafer. 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
 • Aluminium profile frame systems or
panel systems can be used. Other
materials as per requirements are as
Hardwall follows,
Cleanrooms • PVC-surfaces, Polycarbonate, PMMA
Steel plate, Stainless steel , Aluminium
plate and Glass etc.

• These rooms help in saving space.

• Foils are used to provide faster access
Softwall but greater the risk of contamination as
Cleanrooms foils are tough to clean and challenge
constant air flow rate.

Dr Pavika Sharma BPIT 27-10-2023

 NMOS Process
Technology
Step1:
Processing is carried on single crystal silicon of
high purity on which required P impurities are
introduced as crystal is grown. Such wafers are Si-Substrate
about 75 to 150 mm in diameter and 0.4 mm thick
and they are doped with say boron to impurity
concentration of 10 to power 15/cm3 to 10 to the
power 16 /cm3.

Step 2 :
A layer of silicon di oxide (SiO2) typically 1 SiO2
micrometer thick is grown all over the surface of
the wafer to protect the surface, acts as a barrier
to the dopant during processing, and provide a Si-Substrate
generally insulating substrate on to which other
layers may be deposited and patterned.
Dr Pavika Sharma BPIT 27-10-2023
Step 3:
The surface is now covered with the photo
resist which is deposited onto the wafer and spun
to an even distribution of the required thickness.

Step 4:
The photo resist layer is then exposed to
ultraviolet light through masking which defines
those regions into which diffusion is to take place
together with transistor channels. Assume, for
example , that those areas exposed to uv
radiations are polymerized (hardened), but that
the areas required for diffusion are shielded by the
mask and remain unaffected.

Step 5:
These areas are subsequently readily etched away
together with the underlying silicon di oxide so
that theSharma
Dr Pavika waferBPIT surface is exposed in the window 27-10-2023
defined by the mask.
Step 6:
The remaining photo resist is removed and a thin layer of SiO2 (0.1 micro m typical) is grown over
the entire chip surface and then poly silicon is deposited on the top of this to form the gate
structure. The polysilicon layer consists of heavily doped polysilicon deposited by chemical vapour
deposition (CVD). In the fabrication of fine pattern devices, precise control of thickness, impurity
concentration, and resistivity is necessary

Dr Pavika Sharma BPIT 27-10-2023

Step 7:
Further photo resist coating and masking allows the poly silicon to be patterned and then the
thin oxide is removed to expose areas into which n-type impurities are to be diffused to form
the source and drain. Diffusion is achieved by heating the wafer to a high temperature and
passing a gas containing the desired n-type impurity.
Note: The poly silicon with underlying thin oxide and the thick oxide acts as mask during
diffusion the process is self aligning.

Dr Pavika Sharma BPIT 27-10-2023

Step 8:
Thick oxide (SiO2) is grown over all again and is then masked with photo resist and etched to
expose selected areas of the poly silicon gate and the drain and source areas where
connections are to be made. (contacts cut)

Step 9:
The whole chip then has metal (aluminium) deposited over its surface to a thickness
typically of 1 micro m. This metal layer is then masked and etched to form the required
interconnection pattern.

Dr Pavika Sharma BPIT 27-10-2023

Dr Pavika Sharma BPIT 27-10-2023
 CMOS & NMOS Process Technology

Dr Pavika Sharma BPIT 27-10-2023

 CMOS fabrication steps

The CMOS fabrication process flow is conducted using twenty basic fabrication
steps while manufactured using N- well/P-well technology.

Dr Pavika Sharma BPIT 27-10-2023

 Using N-Well

Dr Pavika Sharma BPIT 27-10-2023

Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
 CMOS Processing

(i) Micron rules, in which the layout constraints such as minimum feature sizes and minimum allowable feature
separations are stated in terms of absolute dimensions in micrometers, or,
(ii) Lambda rules, which specify the layout constraints in terms of a single parameter lambda and thus allow linear,
proportional scaling of all geometrical constraints
Dr Pavika Sharma BPIT 27-10-2023
 LOCOS Mask

• LOCOS = LOCal Oxidation of Silicon

• Defines a set of fabrication technologies where,

• the wafer is masked to cover all active regions

• thick field oxide (FOX) is grown in all non-active regions

• Used for electrical isolation of CMOS devices

• Relatively simple to understand so often used to introduce/describe CMOS

fabrication flows

• Not commonly used in modern fabrication

• other techniques, such as Shallow Trench Isolation (STI) are currently more
common than LOCOS
Dr Pavika Sharma BPIT 27-10-2023
 Form N-Well regions NWELL mask

• Grow oxide
• Deposit photoresist
oxide photoresist

p-type substrate

Cross section view

NWELL mask

Layout view

Dr Pavika Sharma BPIT 27-10-2023

 Form N-Well regions
NWELL mask
• Grow oxide
• Deposit photoresist
• Pattern photoresist oxide photoresist
• NWELL Mask
• expose only n-well p-type substrate
areas
Cross section view

NWELL mask

Layout view

Dr Pavika Sharma BPIT 27-10-2023

 Form N-Well regions
• Grow oxide
• Deposit photoresist
• Pattern photoresist oxide
• NWELL Mask
• expose only n-well p-type substrate
areas
Cross section view
• Etch oxide
• Remove photoresist

Layout view

Dr Pavika Sharma BPIT 27-10-2023

 Form N-Well regions
• Grow oxide
• Deposit photoresist
n-well
• Pattern photoresist
• NWELL Mask
• expose only n-well p-type substrate
areas
Cross section view
• Etch oxide
• Remove photoresist
• Diffuse n-type
dopants through
oxide mask layer

Layout view

Dr Pavika Sharma BPIT 27-10-2023

 Form Active Regions
ACTIVE mask
• Deposit SiN over wafer
• Deposit photoresist
over SiN layer n-well
SiN photoresist

p-type substrate

ACTIVE mask

Dr Pavika Sharma BPIT 27-10-2023

 Form Active Regions
ACTIVE mask
• Deposit SiN over wafer
• Deposit photoresist
over SiN layer n-well
SiN photoresist
• Pattern photoresist
• *ACTIVE MASK p-type substrate

ACTIVE mask

Dr Pavika Sharma BPIT 27-10-2023

 Form Active Regions
• Deposit SiN over wafer
• Deposit photoresist
over SiN layer n-well
SiN photoresist
• Pattern photoresist
• *ACTIVE MASK p-type substrate

• Etch SiN in exposed

areas
• leaves SiN mask
which blocks oxide
growth

ACTIVE mask

Dr Pavika Sharma BPIT 27-10-2023

 Form Active Regions
• Deposit SiN over wafer
• Deposit photoresist
over SiN layer n-well

• Pattern photoresist FOX

• *ACTIVE MASK p-type substrate

• Etch SiN in exposed

areas
• leaves SiN mask
which blocks oxide
growth
• Remove photoresist
• Grow Field Oxide
(FOX) ACTIVE mask
• thermal oxidation

Dr Pavika Sharma BPIT 27-10-2023

 Form Active Regions
• Deposit SiN over wafer
• Deposit photoresist
over SiN layer n-well

• Pattern photoresist FOX

• *ACTIVE MASK p-type substrate

• Etch SiN in exposed

areas
• leaves SiN mask
which blocks oxide
growth
• Remove photoresist
• Grow Field Oxide
(FOX) ACTIVE mask
• thermal oxidation
• Remove SiN

Dr Pavika Sharma BPIT 27-10-2023

 Form Gate (Poly
layer)
• Grow thin Gate Oxide
• over entire wafer
• negligible effect on gate oxide
FOX regions

Dr Pavika Sharma BPIT 27-10-2023

 Form Gate (Poly POLY mask
layer)
• Grow thin Gate Oxide
• over entire wafer
gate oxide polysilicon
• negligible effect on
FOX regions
• Deposit Polysilicon
• Deposit Photoresist

POLY mask

Dr Pavika Sharma BPIT 27-10-2023

 Form Gate (Poly POLY mask
layer)
• Grow thin Gate Oxide
• over entire wafer
• negligible effect on gate oxide
FOX regions
• Deposit Polysilicon
• Deposit Photoresist
• Pattern Photoresist
• *POLY MASK
• Etch Poly in exposed
areas
• Etch/remove Oxide
• gate protected by POLY mask
poly

Dr Pavika Sharma BPIT 27-10-2023

 Form Gate (Poly
layer)
• Grow thin Gate Oxide
• over entire wafer
• negligible effect on gate oxide
FOX regions
• Deposit Polysilicon
• Deposit Photoresist
• Pattern Photoresist
• *POLY MASK
• Etch Poly in exposed
areas
• Etch/remove Oxide
• gate protected by
poly

Dr Pavika Sharma BPIT 27-10-2023

 Form pmos S/D PSELECT mask

• Cover with photoresist

PSELECT mask

Dr Pavika Sharma BPIT 27-10-2023

 Form pmos S/D PSELECT mask

• Cover with photoresist

• Pattern photoresist
• *PSELECT MASK

POLY mask

Dr Pavika Sharma BPIT 27-10-2023

 Form pmos S/D
• Cover with photoresist
• Pattern photoresist
• *PSELECT MASK
• Implant p-type p+ dopant p+ dopant
dopants
• Remove photoresist

POLY mask

Dr Pavika Sharma BPIT 27-10-2023

 Form nmos S/D NSELECT mask

• Cover with photoresist

p+ p+ p+

POLY mask

Dr Pavika Sharma BPIT 27-10-2023

 Form nmos S/D NSELECT mask

• Cover with photoresist

• Pattern photoresist p+ p+ p+
• *NSELECT MASK n

POLY mask

Dr Pavika Sharma BPIT 27-10-2023

 Form nmos S/D
• Cover with photoresist
• Pattern photoresist n+ p+ p+ n+ n+ p+
• *NSELECT MASK n
• Implant n-type n+ dopant n+ dopant
dopants
• Remove photoresist

POLY mask

Dr Pavika Sharma BPIT 27-10-2023

 CONTACT mask
Form Contacts
• Deposit oxide
• Deposit photoresist n+ p+ p+ n+ n+ p+

CONTACT mask

Dr Pavika Sharma BPIT 27-10-2023

 CONTACT mask
Form Contacts
• Deposit oxide
• Deposit photoresist n+ p+ p+ n+ n+ p+

• Pattern photoresist n
• *CONTACT Mask
• One mask for both
active and poly
contact shown

CONTACT mask

Dr Pavika Sharma BPIT 27-10-2023

 Form Contacts
• Deposit oxide
• Deposit photoresist n+ p+ p+ n+ n+ p+

• Pattern photoresist n
• *CONTACT Mask
• One mask for both
active and poly
contact shown
• Etch oxide

Dr Pavika Sharma BPIT 27-10-2023

 Form Contacts
• Deposit oxide
• Deposit photoresist n+ p+ p+ n+ n+ p+

• Pattern photoresist n
• *CONTACT Mask
• One mask for both
active and poly
contact shown
• Etch oxide
• Remove photoresist
• Deposit metal1
• immediately after
opening contacts
so no native oxide
grows in contacts
• Planerize
• make top level
Dr Pavika Sharma BPIT 27-10-2023
 METAL1 mask
Form Metal 1 Traces
• Deposit photoresist
n+ p+ p+ n+ n+ p+

METAL1 mask

Dr Pavika Sharma BPIT 27-10-2023

 METAL1 mask
Form Metal 1 Traces
• Deposit photoresist
• Pattern photoresist n+ p+ p+ n+ n+ p+
• *METAL1 Mask n

METAL1 mask

Dr Pavika Sharma BPIT 27-10-2023

 Form Metal 1 Traces
• Deposit photoresist
• Pattern photoresist n+ p+ p+ n+ n+ p+
• *METAL1 Mask n
• Etch metal

metal over poly outside of cross section

Dr Pavika Sharma BPIT 27-10-2023

 Form Metal 1 Traces
• Deposit photoresist
• Pattern photoresist n+ p+ p+ n+ n+ p+
• *METAL1 Mask n
• Etch metal
• Remove photoresist

Dr Pavika Sharma BPIT 27-10-2023

 VIA mask
Form Vias to Metal1
• Deposit oxide
• Planerize oxide n+ p+ p+ n+ n+ p+

• Deposit photoresist n

VIA mask

Dr Pavika Sharma BPIT 27-10-2023

 VIA mask
Form Vias to Metal1
• Deposit oxide
• Planerize n+ p+ p+ n+ n+ p+

• Deposit photoresist n

• Pattern photoresist
• *VIA Mask

VIA mask

Dr Pavika Sharma BPIT 27-10-2023

 Form Vias to Metal1
• Deposit oxide
• Planerize n+ p+ p+ n+ n+ p+

• Deposit photoresist n

• Pattern photoresist
• *VIA Mask
• Etch oxide
• Remove photoresist

Dr Pavika Sharma BPIT 27-10-2023

 Form Vias to Metal1
• Deposit oxide
• Planerize n+ p+ p+ n+ n+ p+

• Deposit photoresist n

• Pattern photoresist
• *VIA Mask
• Etch oxide
• Remove photoresist
• Deposit Metal2

Dr Pavika Sharma BPIT 27-10-2023

 METAL2 mask
Form Metal2 Traces
• Deposit photoresist
n+ p+ p+ n+ n+ p+

METAL2 mask

Dr Pavika Sharma BPIT 27-10-2023

 METAL2 mask
Form Metal2 Traces
• Deposit photoresist
• Pattern photoresist n+ p+ p+ n+ n+ p+
• *METAL2 Mask n

METAL2 mask

Dr Pavika Sharma BPIT 27-10-2023

 Form Metal2 Traces
• Deposit photoresist
• Pattern photoresist n+ p+ p+ n+ n+ p+
• *METAL2 Mask n
• Etch metal

Dr Pavika Sharma BPIT 27-10-2023

 Form Metal2 Traces
• Deposit photoresist
• Pattern photoresist n+ p+ p+ n+ n+ p+
• *METAL2 Mask n
• Etch metal
• Remove photoresist

Dr Pavika Sharma BPIT 27-10-2023

 Form Additional Traces
• Deposit oxide
n+ n+ n+
• Deposit photoresist p+ p+ p+

n
• Pattern photoresist
• Etch oxide
p-type substrate
• Deposit metal
• Deposit photoresist
• Pattern photoresist
• Etch metal
• Repeat for each
additional metal

Dr Pavika Sharma BPIT 27-10-2023

Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
MOS transistor
theory MOS Operation

Dr Pavika Sharma BPIT 27-10-2023

 CIRCUIT SYMBOL (NMOS)
ENHANCEMENT-TYPE: NO CHANNEL AT ZERO GATE
VOLTAGE

D
ID = IS

G B (IB=0, should be reverse biased)

IG = 0

IS G-Gate
D-Drain
S S-Source
B-Substrate or Body

Dr Pavika Sharma BPIT 27-10-2023

Dr Pavika Sharma BPIT 27-10-2023
 Threshold voltage and its dependence on VSB

Dr Pavika Sharma BPIT 27-10-2023

Dr Pavika Sharma BPIT 27-10-2023
MOS device design equations,
MOSFET Operation in linear region

 Assume VGS>VT, At source Voltage=0, At drain Voltage=VDS

 At x, Voltage is V(x), Gate to Channel Voltage is: VGS-V(x)
 Induced channel charge is

where, ƐOX is Oxide Permittivity:3.97xƐO=3.5 x 10^-11F/m, tOX is oxide

thickness.

Dr Pavika Sharma BPIT 27-10-2023

  Drift Current is

,where vn(x) is drift velocity, Qi(x) is charge per unit Area and W is Device width

 With n is mobility and Ɛ(x) is field, V is potential

Dr Pavika Sharma BPIT 27-10-2023

 MOSFET Operation in saturation region

 As the value of the drain-source voltage is further increased, the assumption that the channel voltage is
larger than the threshold all along the channel ceases to hold.
 This happens when VGS -V(x) < VT.
 At that point, the induced charge is zero, and the conducting channel disappears or is pinched off.

Dr Pavika Sharma BPIT 27-10-2023

Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
  No channel exists in the vicinity of the drain region.
 Obviously, for this phenomenon to occur, it is essential that the pinch-off condition
be met at the drain region, or

 Under those circumstances, the transistor is in the saturation region, no longer holds.
The voltage difference over the induced channel (from the pinch-off point to the
source) remains fixed at VGS - VT, and consequently, the current remains constant (or
saturates).

 Replacing VDS by VGS - VT in Eq. above the drain current for the saturation mode.
 It is worth observing that, to a first agree, the current is no longer a function of VDS.
 Notice also the squared dependency of the drain current with respect to the control
voltage VGS.

Dr Pavika Sharma BPIT 27-10-2023

Channel length modulation: the variation in the electric field along the channel as VDS increases. As the drain-source
voltage increases, the electric field near the drain becomes stronger. This strong electric field can cause the depletion
region at the drain junction to extend further into the channel, effectively reducing the channel length. This reduced
channel length allows for higher current flow between the source and drain, resulting in an increase in the drain current,
even in saturation mode.

Dr Pavika Sharma BPIT 27-10-2023

 LONG CHANNEL, ID VS VDS

Dr Pavika Sharma BPIT 27-10-2023

Dr Pavika Sharma BPIT 27-10-2023
MOSFET scaling and small geometry
effects

Dr Pavika Sharma BPIT 27-10-2023

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Dr Pavika Sharma BPIT 27-10-2023
 SHORT CHANNEL DEVICES:

Dr Pavika Sharma BPIT 27-10-2023

Dr Pavika Sharma BPIT 27-10-2023
MOSFET capacitances

Dr Pavika Sharma BPIT 27-10-2023

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NMOS inverter

Dr Pavika Sharma BPIT 27-10-2023

Dr Pavika Sharma BPIT 27-10-2023
Dr Pavika Sharma BPIT 27-10-2023
 Moore’s Law

Moore’s Law explains the empirical regularity that the number of transistors on an IC approximately
doubles every two years. In turn, as advancement on number of transistors is made, technological aspects
like the processing speed etc. also advances.
Figure shows the Moore’s 1st law Prediction and Actual Growth
Dr Pavika Sharma BPIT 27-10-2023
 Multi-gate MOSFETs

Dr Pavika Sharma BPIT 27-10-2023

Dr Pavika Sharma BPIT 27-10-2023
 Non-Conventional MOSFET

Performance enhancement of the MOSFET along with scaling the device dimensions is a
major point of concern below the 50nm technology node! To achieve this different non-
conventional device design technologies and architectures have been proposed by the
researchers for &' MOSFET!
• Double Gate MOSFET is a novel device introduced in
1980s to overcome the physical limitations imposed by
the bulk MOSFET! The main idea of a double gate
MOSFET (DGFET) is to have a Si channel of very small
width and to control the Si-channel by applying gate
contacts to both sides of the channel!

• It consists of 2 gates namely front gate and bottom

gate which can be controlled either symmetrically or
asymmetrically! Because of the multi
gate functionality this device is having superior control
over the channel and provides excellent
characteristics! The source and drain regions are
heavily doped (Ntype, N+, Ptype, P+) and the channel
is lightly doped -Ntype, P, Ptype, N) in DG MOSFET!

• Pavika
Dr TheSharma
double-gate
BPIT structure is comprised of a conducting 27-10-2023
channel surrounded by gate electrodes on either side
• This architecture eliminates the interface
irregularities of oxide with Si channel.
• GSDG MOSFET refers to Gate insulator Stack
double gate MOSFET! (It consists of 2 layers of
dielectrics with SiO2 in contact with Si channel
and a High-k layer on the SiO2 layer as a gate
oxide!
• The presence of High-k dielectric layer improves
the oxide capacitance which causes high drive
current and transconductance than DG MOSFET!

Dr Pavika Sharma BPIT 27-10-2023

 Technology Nodes & ITRS

Dr Pavika Sharma BPIT 27-10-2023

 PARAMETERS OF INTEGRATED
CIRCUIT TECHNOLOGY

• Technology Node-The minimum half-pitch of custom-layout metal interconnect is most

representative of the process capability enabling high-density integrated circuits and is
selected to define an ITRS Technology Node. For each Node, this defining metal half-pitch
is taken from whatever product has the minimum value
• Other parameters are also important for characterizing integrated circuit technology. For
example, in the case of microprocessors, physical bottom gate length is most
representative of the leading-edge technology level required for maximum performance.
• Each technology node step represents the creation of significant technology progress in
metal half-pitch---approximately 70% of the preceding node, 50% of the two preceding
nodes.

Dr Pavika Sharma BPIT 27-10-2023

 CHIP AND PACK- PHYSICAL AND ELECTRICAL
ATTRIBUTES

• Number of Chip I/Os - total Pads-the maximum number of chip signal I/O pads plus
power and ground pads permanently connected to package plane for functional or test
purposes, or to provide power/ground contacts

• Number of Chip I/Os- Total( Peripheral) Pads- the maximum number of chip signal I/O
plus power and ground pads for products with contacts only around the edge of a chip

• Pad Pitch- The distance, center-to-center, between pads, whether on the peripheral edge
of a chip, or in array of pads across the chip.

• Number of Package Pins/Balls-the number of pins or solder balls presented by the

package for connection to the board (may be fewer than the number of chip-to-package
pads because of internal power and ground planes on the package plane or multiple chips
per package).
Dr Pavika Sharma BPIT 27-10-2023
 CHARACTERISTICS OF MAJOR
MARKETS
• Moore’s Law- historic observation by Intel executive Gordon Moore:
• Market demand for functionality per chip doubles ever 1.5 to 2 years.
• Microprocessor performance should also double every 1.5 to 2 years as well.
• Has been consistent with market trend and key indicator of successful leading-edge semi conductor
products and companies for the last 20 years.

Note: Corollary to Moore’s law suggest that to be competitive manufacturing productivity

improvements must also enable the cost-per-function to decrease by -29% per year.
Historically when functionality doubled every 1.5 years, the cost-per-chip could double
every six years and still meet the cost-per-function reduction requirement. If functionality
doubles only every three years, as suggested by consensus, DRAM and MPU models, then
manufacturing cost per chip must remain flat.
Dr Pavika Sharma BPIT 27-10-2023
 AFFORDABLE PACKAGED UNIT
COST/FUNCTION
• Final cost is in micro-cents of the cost of a tested and packaged
chip divided by functions/Chip.
• Affordable costs are calculated from historical trends of affordable
average selling prices less an estimated gross profit margin of
approximately 35% for DRAMs and 60% for MPUs.
• The affordability per function is a guideline of figure market “tops-
down” needs, and as such, was generated independently from the
chip size and function density.

Dr Pavika Sharma BPIT 27-10-2023

 AFFORDABLE PACKAGED UNIT
COST/FUNCTION
Affordability requirements are expected to be achieved through combinations of :
1) increased density and smaller chip sizes from technology and design improvements
2) increasing wafer diameters
3) decreasing equipment cost-of-ownership
4)increasing equipment overall equipment effectiveness
5)reduced package and test costs
6) improved design tool productivity
7) enhanced product architecture and integration

Dr Pavika Sharma BPIT 27-10-2023

 AFFORDABLE PACKAGED UNIT
COST/FUNCTION
• Cost-Performance MPU- MPU product optimized for maximum performance and
the lowest cost by limiting the amount of on-chip SRAM level-two(L2) caches.
• Logic functionality and L2 cache typically double every three-year generation
• High-Performance MPU- MPU product optimized for maximum system performance
by combining a single or multiple CPU cores with a large level-two SRAM.
• Logic functionality and L2 cache typically double every three-year technology
generation by doubling the number on-chip CPU and associated memory.

Dr Pavika Sharma BPIT 27-10-2023

 OTHER ATTRIBUTES

Chip Frequency (MHz)

• On-Chip, Local Clock, High-performance- On-chip clock frequency of high-performance, lower
volume microprocessors in localized portions f the chip.
• Chip-To-Board (Off-chip) Speed (High-performance, Peripheral Buses)-Maximum signal I/O frequency
to board peripheral buses of high and low volume logic devices

• Lithographic Fields Size-Maximum single step or step-and-scan exposure area of lithographic tool at
the given technology node. The specification represents the minimum specification that a
semiconductor manufacturer might specify for a given technology node.
• Maximum Number of Wiring Levels- On-chip interconnect levels including local interconnect, local
and global routing, power and ground connections and clock distribution.

Dr Pavika Sharma BPIT 27-10-2023

Dr Pavika Sharma BPIT 27-10-2023