CMOS Digital Integrated Circuits

Chapter 10
Semiconductor Memories

Copyright © 2014 McGraw-Hill Education. Permission required for reproduction or display.

1
 10.1 Introduction
 Design issue
 Area efficiency cost per bit
 Access time speed
 Power consumption low-power

2 © CMOS Digital Integrated Circuits – 4 th Edition

 10.1 Introduction
 Semiconductor memory types
Semiconductor Memories

Volatile Non-volatile

Dynamic RAM Static RAM Programmable ROM

Mask (Fuse) ROM
(DRAM) (SRAM) (PROM)

Erasable PROM Electrically Erasable

(EPROM) PROM (EEPROM)

• Flash Memory
• Ferroelectric RAM (FRAM)
• Magnetoresistive RAM(MRAM)
• Resistive RAM(RRAM)
• Phase-change RAM(PCRAM)
• Spin Torque Transfer RAM(STT)

3 © CMOS Digital Integrated Circuits – 4 th Edition

 Characteristic Summary of Memory
Devices
Memory type
DRAM SRAM UV EPROM EEPROM Flash FRAM
Data volatility Yes Yes No No No No
Data refresh Require
No No No No No
operation d
Cell structure 1T-1C 6T 1T 2T 1T 1T-1C
Cell size(F2) 4~5(NAND)
6~8 80~100
(F: min. feature size) 9~10(NOR)
Cell density High Low High Low High High
Power consumption High High/low Low Low Low High
Read speed (latency) ~50 ns ~10/70 ns ~50 ns ~50 ns ~50 ns ~100 ns
~(10 μs-1
Write speed ~40 ns ~5/40 ns ~10 μs ~5 ms ~100 ns
ms)
Endurance High High High Low High High
Cost Low High Low High Low Low
In-system writability Yes Yes No Yes Yes Yes
Power supply Single Single Single Multiple Single Single
Smart
Memory
Main Game card,
Application example Cache/PDAs ID card card solid-
4 memory ©machines
CMOS Digital Integrated Circuits digital
– 4 th Edition
state disk
camera
Equivalent Circuits of Memory Cells(1)

(a) DRAM (b) SRAM

5 © CMOS Digital Integrated Circuits – 4 th Edition

Equivalent Circuits of Memory Cells(2)

(c) Mask ROM (d) EPROM (e) FRAM

6 © CMOS Digital Integrated Circuits – 4 th Edition

Conceptual RAM Array Organization

7 © CMOS Digital Integrated Circuits – 4 th Edition

10.2 Dynamic Random Access Memory

Typical configuration of DRAM chip

(1.6Gbps 4Gb 30nm LPDDR3 w/ 8 banks)
chip size performance
The number of cells per word and bit lines Pin
assignment
8 © CMOS Digital Integrated Circuits – 4 th Edition
Definition and Function of DRAM Pins
Pin name Definition Function
Reference system clock for the operation and
CLK Clock input
data communication
CKE Clock Enable Control the clock input
Activate the DRAM device from a memory
CS Chip Select
cluster
Latch row address and start the cell core
RAS Row Address Strobe
operation
Latch column address and start the data
CAS Column Address Strobe
communication operation
WE Write Enable Activate the write operation
A0 to A14 Address input Select a data bit
DQ0 to DQ15 Data input and output Communicate data with external devices
DQ Mask for Upper
DQMU/DQML Mask byte data from the operations
(Lower) Byte
VDD/VSS Power pins Power for DRAM core and peripheral circuits
VDDQ/VSSQ Power pins Power for DQ circuits
NC No connection
9 © CMOS Digital Integrated Circuits – 4 th Edition
Historical Evolution of DRAM Cell(1)
 Four-transistor DRAM cell

 Operations are similar to SRAM cell

 Two storage nodes
 Periodically refresh is required
 Non-destructive read operation

 Three-transistor DRAM cell

 One storage node

 One Tr. each for “read” and “write”
 Non-destructive read operation
 Two bit lines and two word lines
(additional contacts increase area)

10 © CMOS Digital Integrated Circuits – 4 th Edition

Historical Evolution of DRAM Cell(2)
 Two-transistor DRAM cell

 Explicit storage cap.

 Destructive read operation
(share with the bit line)
 Two bit lines and one word line

 One-transistor DRAM cell

 Industry-standard DRAM cell

 Destructive read operation
(share with the bit line)
Charge restoring operation required

11 © CMOS Digital Integrated Circuits – 4 th Edition

 DRAM Cell Types
 With only one transistor and one capacitor
 Smallest area of the all DRAM cells.
 Destructive “read” operation
major effort : large cap. cell with minimized
area

(a) DRAM cell with a stacked cap. (b) DRAM cell with a trench
cap.
12 © CMOS Digital Integrated Circuits – 4 th Edition
 Feb 12 Lecture on Memories (Continued)

13 © CMOS Digital Integrated Circuits – 4 th Edition

 Bio-inspired Computing Using ReRAM

14 © CMOS Digital Integrated Circuits – 4 th Edition

Operation of Three-Transistor DRAM
Cell
 Typical 3-T DRAM cell and voltage waveforms

15 © CMOS Digital Integrated Circuits – 4 th Edition

 Precharge Events
Base on two-phase non-
overlapping clock scheme

Φ1 : precharge phase

Φ2 : active phase

Precharge signal PC goes up

MP1 and MP2 are activated

C2 and C3 are charged up

(Steady-state values)
16 © CMOS Digital Integrated Circuits – 4 th Edition
Write “1” and Read “1” Operations
 Write “1”
 DATA is low Din remains high
 M1 turns on (WS is high)

C2 shared with C1
 C1 charge up to high
(M2 is conducting)

 Read “1”
 RS is high M3 turns on
 M2 and M3 create conducting path
from C3 to GND
 C3 discharges
 Non-destructive read operation

17 © CMOS Digital Integrated Circuits – 4 th Edition

Write “0” and Read “0” Operations
 Write “0”
 DATA is high Din goes low
 M1 turns on (WS is high)
 C1 discharges
(M2 turns off)

 Read “0”
 RS is high M3 turns on
 No conducting path
 C3 does not discharge

18 © CMOS Digital Integrated Circuits – 4 th Edition

Operation of One-Transistor DRAM Cell
 One explicit storage cap. and one access
transistor
 The most widely used storage structure
 Bit lines are folded and precharged to half-VDD
improve noise-immunity & reduce power
consumption
 Operation : “read”, “write”, “refresh”

19 © CMOS Digital Integrated Circuits – 4 th Edition

 1-T DRAM Structure
 DRAM cell array with control circuits
 Latch amplifier to sense the small signal difference
 Bit lines and sensing nodes set to half-VDD through equalizer

20 © CMOS Digital Integrated Circuits – 4 th Edition

PEQ/PSAEQ
VDD
DRAM Read Operation
PISOi
VPP

 CS shared with CBL(=initially half VDD)

VDD
PISOi/PISOj
PISOj

VPP

CS VDD
Word Line
charge sharing between the cell and bit line capacitances
V 
VDD
S cell data restoring BL CBL  CS 2
BL/BLB 1/2VDD

activation of
BLB
 CS : VDD ½VDD+ΔV (destructive)
VDD bit line sense amplifier
PSA
 BL and BLB voltage difference amplified
VDD
PSAB
 BLB GND, BL VDD
VDD
Column Select
storage node is recovered (restoring)
 Column switch is enabled by column
BL_IO
BL_IO/BL_IOB VDD
BL_IOB

Dout_IO

Dout_IO/
Dout_IOB
VDD
decoder (BL BL_IO, BLB BL_IOB)
(a)  Read Amp. amplifies the voltage difference

 VPP=VDD+Vth for full charge restoration

 PSA and PSAB are sequentially activated to
reduce charge injection and short circuit current

21 © CMOS Digital Integrated Circuits – 4 th Edition

 DRAM Write Operation
 Identical sequence to normal
read operation
 Strong write driver (buffer)
to drive BL_IO, BL_IOB line
cap.

faster than read operation

 Column switch is selected by
column decoder
 Bit line and cell data
changed

22 © CMOS Digital Integrated Circuits – 4 th Edition

 Asynchronous DRAM Mode(1)

 single bit access (different row and column addresses)

 Operation uses address multiplexing scheme (RAS and CAS)
reduce the chip package size
 RAS pull down operation start
 Falling edge of CAS data (from same word line) selected
 RAS, CAS precharge before new data access
 tRAC : memory read latency, time to read data from falling of
RAS
 Length of word line is determined by refresh cycle constraint

23 © CMOS Digital Integrated Circuits – 4 th Edition

 Asynchronous DRAM Mode(2)
 page access
 keep the row address
 read cell of same row address
 faster read operation

 extened data-out(EDO)
 new column address is
captured at rising edge of
CAS
 Read data maintain during
precharge time
 Fastest read opertaion

24 © CMOS Digital Integrated Circuits – 4 th Edition

 Synchronous DRAM Mode
 Four bit burst read
 Read frequency improve with
use of the system clock
 At falling edge, control signal
and addresses become active
 Pipelined based on clock to
improve throughput
 Use both of edges to improve
bandwidth (Dual Data Rate)
 Serial mode read
 Use small signal swing and
clock recovery scheme to
maximize the frequency
 Send control input as packet
 Send out data in a serial form

25 © CMOS Digital Integrated Circuits – 4 th Edition

 Leakage Currents in DRAM Cells
 Contact and bit line share by
two adjacent cells
I leakage I sub  I tunneling  I j  I cell  to  cell
Isub: leakage through cell transistor
Itunneling: tunneling through thin dielectric
Ij: junction leakage at storage node
Icell-to-cell: leakage across the field oxide

 Isub depend on Vth

increase VSB to reduce Isub
 Itunneling is a serious issue
because thickness of dielectric is
reduced to increase cell cap.

26 © CMOS Digital Integrated Circuits – 4 th Edition

 Refresh Operation
 ROR(RAS-only refresh) refresh
 Read and restore operation
 Does not send data out
 similar to normal read
operation
ROR refresh mode
 CBR(CAS-before-RAS) refresh
 row address generated by on-
chip counter
 performed periodically
CBR refresh mode  Self refresh
 period set according to
operating condition
 row address and control signal
generated by internal circuit
Self refresh mode

27 © CMOS Digital Integrated Circuits – 4 th Edition

 DRAM Input/Output Circuits(1)
 Logic level of system board and memory chip are different
required to convert logic levels input/output buffers

 Input buffers

inverter type latch type differential amp type

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Characteristic Comparison of Input
Buffers
Buffer type

Inverter Latch Differential

Logic threshold determination By WP/WN

By Vref By Vref
(VIH and VIL) ratio

Speed Slow Fastest Fast

Standby current Small Smallest Large

Sensitivity to VDD and

Large Small Small
temperature

Noise immunity Bad Good Good

Precharge and
Constraint None activation signals None
needed

29 © CMOS Digital Integrated Circuits – 4 th Edition

 DRAM Input/Output Circuits(2)
 Memory output buffers
 Need to drive large cap.
 Keep a high-impedance when chip is not selected
to prevent interference of output

PMOS pull-up structure NMOS pull-up structure

30 © CMOS Digital Integrated Circuits – 4 th Edition

 DRAM Decoder(1)
 To select cell from 22M memory array, M address bits are
needed
 Practically, M transistors in series is impossible
decoding scheme is composed of pre and main decoder

31 © CMOS Digital Integrated Circuits – 4 th Edition

 DRAM Decoder(2)
 VPP for full restoration
 Output of predecoder
boosted by level shifter
 Self-bootstrapped driver
for transferring to highly
cap. without signal
degradation

 Voltage of C when main

decoder is selected CMN 2
V V  V V  V  VPP
C PP DD TN
CMN 2  CCparasitic

32 © CMOS Digital Integrated Circuits – 4 th Edition

 Voltage Sense Amplifiers
 To detect signal difference on data lines
 Current-mirror differential
 Popular and good common-mode rejection
ratio
 Large area and large power consumption

 Full CMOS latch type

 High speed, small area and low power
 Precharge signal required
 operation cannot be reversed

 Semilatch type
 Between current-mirror type and full CMOS latch
type

33 © CMOS Digital Integrated Circuits – 4 th Edition

 Internal Voltage Regulator Circuit
 Lowering voltage to reduce power consumption
 VINT(internal voltage generator)
reduce operating current

34 © CMOS Digital Integrated Circuits – 4 th Edition

 Half VDD Voltage Generator
 Folded bit line structure with half VDD sensing scheme
 Improve noise immunity and low power consumption
 Reduce electric field across thin dielectric

bias ckt driver simulated output waveforms

35 © CMOS Digital Integrated Circuits – 4 th Edition

 Negative Substrate Bias Voltage
Generator(1)
 Subthreshold current is major source of charge
decay
 Negative voltage substrate increase threshold
voltage
reduce load cap. of bit
line

VT
 VSB
VSB

36 © CMOS Digital Integrated Circuits – 4 th Edition

 Negative Substrate Bias Voltage
Generator(2)

Timing diagram

Circuit diagram

Simulated waveforms

37 © CMOS Digital Integrated Circuits – 4 th Edition

10.3 Static Random Access Memory(1)
 Stored data can be retained indefinitely
 Simple latch with two stable operating points
 Two access switches to connect 1-bit SRAM
 Poly resistor load inverter structure is more compact cell size
(resistor stack on top of cell)
 Load R trade off : low power wider noise margin, high
speed

Symbolic representation Generic topology of SRAM Resistive-load SRAM

38 © CMOS Digital Integrated Circuits – 4 th Edition

10.3 Static Random Access Memory(2)
 Depletion-load NMOS SRAM
 Six-transistor
(one poly and one metal layer)
 Cell size relatively small
 Static characteristics and noise
margins better than resistive-load
cell
 Static power consumption

 Full CMOS SRAM

 Most popular
 Lowest static power
 Superior noise margins and switching
speed

39 © CMOS Digital Integrated Circuits – 4 th Edition

 Full CMOS SRAM Cell(1)
 Very small static power dissipation (limited by leakage
current)
 High noise immunity (large noise margin)
 Ability to operate at lower supply
 Disadvantage : cell area slightly larger, latch-up
phenomena

40 © CMOS Digital Integrated Circuits – 4 th Edition

 Full CMOS SRAM Cell(2)

Layout of CMOS SRAM cell Layout of a 4-bit X 4bit SRAM

array, consisting of 16 CMOS SRAM
cells

41 © CMOS Digital Integrated Circuits – 4 th Edition

CMOS SRAM Cell Design Strategy(1)
 Two basic requirements which dictate W/L ratio
 Non-destructive data read operation
 Modify stored data during write phase

 Read Operation (0 stored)

 M3 and M1 conduct some current
 VCc drops slightly and V1 increases
 not to turn on M2 V1,max VT ,2
 M3 in Saturation and M1 in linear
kn ,3 kn ,1
(VDD  V1  VT ,n ) 2  (2(VDD  VT ,n )V1  V12 )
2 2
W 
 
kn ,3  L  3 2(VDD  1.5VT ,n )VT ,n
 
kn ,1 W  (VDD  2VT ,n ) 2
 
 L 1

42 © CMOS Digital Integrated Circuits – 4 th Edition

CMOS SRAM Cell Design Strategy(2)

 Write 0 operation (initially, 1 was stored at node 1)

 V1 must be reduced below VT,2 M2 turns off, V2 rises and V1 falls
 When V1=VT,n, M3 in linear k p ,5 k
(0  VDD  VT , p ) 2  n ,3 (2(VDD  VT ,n )VT ,n  V 2T ,n )
& M5 in saturation 2 2
W 
 
k p ,5 2(VDD  1.5VT ,n )VT ,n  L  5 n 2(VDD  1.5VT ,n )VT ,n
  
kn ,3 (VDD  VT , p ) 2 W  p (VDD  VT , p ) 2
 
 L 3

43 © CMOS Digital Integrated Circuits – 4 th Edition

 Memory Structure of SRAM
 Word line selected by row
address
 Cell data kept during read
operation
 Boosted voltage not required
 Address multiplexing scheme
is not used (fast access time
than DRAM)
 Depend on applications
 ultra low power : load
transistor turns off during read
operation
 high speed : remains on

44 © CMOS Digital Integrated Circuits – 4 th Edition

 Operation of SRAM
 Read operation
 Word line enable
 One bit line discharge
(voltage change of bit line is very
small)
 Sense amp. detect the voltage
difference on bit line
 Multi-stage amp. is used to improve
read speed
 Write operation
 Word line selected by row address
 Write buffer write data into cell
 Write buffer has larger current
driving capability than cell
 Write is faster than read

45 © CMOS Digital Integrated Circuits – 4 th Edition

 SRAM Read Operation
 TTL level converts into CMOS level signal
 Internal voltage regulator to reduce power
dissipation
to improve reliability

46 © CMOS Digital Integrated Circuits – 4 th Edition

 Leakage Currents in SRAM Cells
 Major portion of standby current
 Standby power is key parameter for low power design
 High threshold
reduction of leakage degradation of
performance

Ij : junction current
data “1” to substrate
Insub and Ipsub : subthreshold leakage
turn off NMOS and PMOS
Itunneling : tunneling current
cross thin gate oxide

47 © CMOS Digital Integrated Circuits – 4 th Edition

 SRAM Read/Write Circuits
 Current-mode sense amp widely
used in SRAM

improve signal sensing speed

independent of bit line cap.
 Signal line connect to source of
latch transistor
 Current difference appears on DL
and DL
 Open-loop gain
g m (m3) g m (m4)
Gainopen  loop 
g m (m1) g m (m2)
 Current-mode sense amp:
Drawback- larger power
consumption

48 © CMOS Digital Integrated Circuits – 4 th Edition

 SRAM Cell at Low Supply Voltage
 SRAM cell susceptible to variabilities
 Due to minimum device size to a minimize area
 Threshold voltage variation covered in Ch. 3 plus layout
induced threshold voltage variation
 PMOS pair (M5, M6) in SRAM cell- different VT due to NBTI
 NMOS pair (M1, M2) in SRAM cell- different VT due to PBTI

 Static noise margin (SNM) word line

 A noise tolerant voltage before

+V - inv
the stored data flip n R

 Equivalent ckt to measure ① ②

SNM bit line inv -V +

L bit line n

 6-T SRAM cell at low supply

Vn: DC noise, SNM: min. DC noise which
voltage degrades SNM flips the state of SRAM cell during read
operation
49 © CMOS Digital Integrated Circuits – 4 th Edition
 SNM Variation due to DC Noise
 How to measure SNM graphically

 SNM: The length of side of the smaller nested square in the two
openings of butterfly curve
 Before two Vns are fed: SNM=VS
 After Vns are fed: stable point A and unstable point B meets at D
 More Vns are applied: one common point C & the stored bits are
flipped
50 © CMOS Digital Integrated Circuits – 4 th Edition
 SRAM Cell Writability
 Write-trip point
 A metric for writability
 Max. bit line voltage to
flip the state of the SRAM
cell
 Primarily determined by
the pull-up ratio of SRAM
cell (Ex: (W/L)5/(W/L)3 )
 Variability tolerant 6T
SRAM cell
 Trade off bw. read
stability and writability
 M3 & M 4 :
SNM , writability
51 © CMOS Digital Integrated Circuits – 4 th Edition
 8T SRAM Cell
 No secondary power
supplies
 Decouples the SRAM
cell nodes from the bit
line which enables
balancing the read &
write modes
 Read operation doesn’t
affect the stored data
 6T cell has the worst
SNM in read operation
where the pass gate
transistor increases the
voltage at the ‘0’ stored

52 © CMOS Digital Integrated Circuits – 4 th Edition

 10.4 Nonvolatile Memory
 Simple combinational Boolean network
 Only one word line selected at a time
 Active transistors exist at cross point
 Dynamic ROM
 use periodic precharge signal to reduce static power

53 © CMOS Digital Integrated Circuits – 4 th Edition

 Layout of NOR ROM Array(1)
 Initially, NMOS at every row-column intersection
 ‘1’-bits are realized by omitting drain or source
connection
or gate electrode of corresponding NMOS

Layout example of a NOR ROM array

54 © CMOS Digital Integrated Circuits – 4 th Edition
 Layout of NOR ROM Array(2)
 In reality, metal column lines laid out directly on
top of diffusion column to reduce horizontal
dimension

Layout of the 4-bit X 4-bit NOR ROM array (pp. 46)

55 © CMOS Digital Integrated Circuits – 4 th Edition
 Implant-mask Programmable NOR
ROM
 Every two rows share a common ground
connection
 Every metal to diffusion contact shared by two
adjacent devices

56 © CMOS Digital Integrated Circuits – 4 th Edition

 4-bit x 4-bit NOR ROM Array
 Based on implant-mask programming
 Raised threshold voltage >VOH “1”-bit
 Non-implanted “0”-bit
 higher core density (smaller silicon area per
stored bit)

57 © CMOS Digital Integrated Circuits – 4 th Edition

 4-bit x 4-bit NAND ROM Array
 Bit line : depletion-load NAND gate
 Deactivated transistor “1”-bit
 Shorted or on transistor “0”-bit

58 © CMOS Digital Integrated Circuits – 4 th Edition

Implant-mask layout of NAND ROM
 Lowered threshold voltage < 0V “0”-bit
 Much more compact than NOR ROM
 Access time is slower than NOR ROM

59 © CMOS Digital Integrated Circuits – 4 th Edition

 Design of Row and Column
Decoders(1)
 Select a particular memory location in array
 Row address decoder example

60 © CMOS Digital Integrated Circuits – 4 th Edition

 Design of Row and Column
Decoders(2)
 ROM array and row decoder (two adjacent NOR
arrays)

61 © CMOS Digital Integrated Circuits – 4 th Edition

 Row Decoder for NAND ROM
 Lower voltage for logic “0”
 Realized using same layout strategy as memory
array

62 © CMOS Digital Integrated Circuits – 4 th Edition

 Column Decoder(1)
 Using NOR address decoder and NMOS pass
transistor
 Only one pass transistor turned on at a time
 2M(M+1) transistors required

63 © CMOS Digital Integrated Circuits – 4 th Edition

 Column Decoder(2)
 Binary selection tree decoder
 NOR address decoder not needed
Reduce the number of transistors
significantly
 But, long data access time

64 © CMOS Digital Integrated Circuits – 4 th Edition

 Example 10.1(1)
 Analyze the access time of a 32-kbit NOR ROM
array
nCox 20  A / V 2
Cox 3.47  F / cm 2
Poly sheet resistance 20 / square

65 © CMOS Digital Integrated Circuits – 4 th Edition

 Example 10.1(2)
 Assume 7 row address bits and 8 column address bits
(128 rows and 256 columns)
 Calculate row resistance and capacitance

Crow Cox W L 10.4 fF / bit

Rrow (# of squares ) ( Poly sheet resistance) 60 / bit
 Calculate row access time
trow 0.38 RT CT 15.53ns

RT  
all columns
Ri 15.36k

CT  
all columns
Ci 2.66 pF

66 © CMOS Digital Integrated Circuits – 4 th Edition

 Example 10.1(3)
 A more accurate delay: Elmore time constant for RC
ladder circuits
256 k
trow  R jk Ck 20.52ns where R jk  R j
k 1 j 1

 Calculate column access time

Ccolumn 128 (C gd ,driver  Cdb ,driver )

1.5 pF
where C gd ,driver  Cdb ,driver 0.0118 pF / word line

128-input NOR gate

representation
67 © CMOS Digital Integrated Circuits – 4 th Edition
 Example 10.1(4)
 To calculate column access time, consider the worst-
case signal propagation delay τPHL for below inverter

tcolumn 18ns (using eq. 6.18: tPHL)

taccess trow  tcolumn 38.5ns

68 © CMOS Digital Integrated Circuits – 4 th Edition

 10.5 Flash Memory
 One transistor with floating gate
 Memory cell can have two states (two threshold)
 Electron accumulated at the floating gate higher threshold “1”
state
 Electron removed from the floating gate lower threshold “0” stat

Hot electron injection mechanism Fowler-Nordheim tunneling mechanism

(Data programming) (Data erasing)
69 © CMOS Digital Integrated Circuits – 4 th Edition
Equivalent Capacitive-Coupling Circuit
 VFG by capacitive coupling
after VCG & VD applied
QFG CFC C
VFG   VCG  FD VD
Ctotal Ctotal Ctotal
Ctotal CFC  CFS  CFB  CFD

 min. VCG to turn on the

control gate transistor
Ctotal Q C
VT (CG )  VT ( FG )  FG  FD VD
QFC : charge stored at floating gate CFC CFC CFC
Ctotal : total cap.
QFG
VT (CG ) 
CFC
CFC : cap. between floating and control gate
CFS, CFB and CFD : cap. between floating gate and source, bulk and drain
VCG and VD : voltage at control gate and drain
VT(FG) : threshold voltage to turn on the floating gate transistor

70 © CMOS Digital Integrated Circuits – 4 th Edition

 I-V Characteristic of Flash Memory
 Low and high threshold voltages for control gate voltage

71 © CMOS Digital Integrated Circuits – 4 th Edition

 NOR Flash Memory Cell
 Bias conditions and configuration of NOR Cells

 F-N tunneling mechanism for erase operation

 Hot-electron injection mechanism for programming operation

72 © CMOS Digital Integrated Circuits – 4 th Edition

 Bias Conditions of NOR Cell
Operation

Signal
Erase Programming Read

Bit line 1 Open 6V 1V

Bit line 2 Open 0V 0V

Source line 12V 0V 0V

Word line 1 0V 0V 0V

Word line 2 0V 12V 5V

Word line 3 0V 0V 0V

73 © CMOS Digital Integrated Circuits – 4 th Edition

 NAND Flash Memory Cell
 Cross-section view and configuration of NAND
cells

 F-N tunneling mechanism for erase

 F-N tunneling mechanism for program
 Slower programming and read speed
but smaller area than NOR cell structure

74 © CMOS Digital Integrated Circuits – 4 th Edition

 Bias Conditions of NAND Cell
Operation

Signal Erase Programming Read

Bit line 1 Open 0V 1V

Bit line 2 Open 0V 1V
Select line 1 Open 5V 5V
Word line 1 0V 10V 5V
Word line 2 0V 10V 5V
Word line 3 0V 10V 5V
Word line 4 0V 10V 5V
Word line 5 0V 20V 0V
Word line 6 0V 10V 5V
Word line 7 0V 10V 5V
Word line 8 0V 10V 5V
Select line 2 Open 0V 5V
Source line Open 0V 0V
p-well 2 20V 0V 0V
n-sub 20V 0V 0V

75 © CMOS Digital Integrated Circuits – 4 th Edition

Comparison between NOR and NAND
NOR NAND

Erase method F-N tunneling F-N tunneling

Programming
Hot electron injection F-N tunneling
method
Erase speed Slow Fast

Program speed Fast Slow

Read speed Fast Slow

Cell size Large Small

Scalability Difficult Easy

Application Embedded system Mass storage

76 © CMOS Digital Integrated Circuits – 4 th Edition

 Multilevel Cell Concept
 Effective memory density can be improved
 Possible state number limited by
 Available charge range
 Accuracy of programming and read operations
 Disturbance of state over time

Threshold voltage distribution of 2bits/cell

storage
77 © CMOS Digital Integrated Circuits – 4 th Edition
 Flash Memory Circuit
 On-chip charge pump used to generate programming
voltage
 Chain of diode and cap. to charge or discharge each half
Vout Vin  (VDD  VT ( MN1))    (VDD  VT ( MNn))
cycle

78 © CMOS Digital Integrated Circuits – 4 th Edition

 10.6 Ferroelectric Random Access
Memory
 Hysteresis characteristic of a ferroelectric cap.

 Total charge varies as function of applied voltage

79 © CMOS Digital Integrated Circuits – 4 th Edition

 Structure and Operation of FRAM
 Similar to DRAM except plate line

 Step-sensing scheme

C1
V1  VDD
C1  CBL
C0
V0  VDD
C0  CBL
C1 and C0 : linearly modeled ferroelectric cap

80 © CMOS Digital Integrated Circuits – 4 th Edition

 Problems of FRAM
 Step-sensing scheme cause reliability issues
 Pulse sensing scheme also used with read speed penalty

 Fatigue
 Capacitance charge gradually degraded with repeated
use

 Imprint
 Ferroelectric cap tends to stay at one state preferably
when state maintained for a long time

81 © CMOS Digital Integrated Circuits – 4 th Edition