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CADD Unit 2

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Vandana Ch
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34 views29 pages

CADD Unit 2

Uploaded by

Vandana Ch
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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FPGA

FPGA
CONT..
Architecture
Cont..
Configurable Logic Block
 Logic blocks implement the logical functions required by the design and consist of
various components such as transistor pairs, look-up tables (LUTs), flip flops, and
multiplexers.
 You can think of logic blocks as separate modules like lego blocks which can operate in
parallel. Unlike a lego block, a logic block is configurable i.e. its internal state can be
controlled and you can hook these together by programming the interconnects in
order to build something meaningful.
Programmable Interconnects
 This hierarchy of programmable interconnection is used for allocating resources
among configurable logic blocks (CLBs); where routing paths contain wire segments of
varying lengths that can be connected via anti-fuse or memory-based techniques.
 Each CLB is tied to a switch matrix to access the general routing structure. The switch
matrix provides programmable multiplexers, which are used to select the signals in a
given routing channel and thereby connect vertical and horizontal lines.
Programmable IO Block

 Lastly, the I/O blocks (IOBs) are used to interface the CLBs and routing architecture to
the external components.
 In earlier FPGAs, there was no processor to run any software; hence implementing an
application implied designing the circuit from scratch. So, we could have configured an
FPGA to be as simple as an OR gate or as complex as the multi-core processor.
 But we have come a long way since XC2064 and the basic FPGA architecture has
developed through the addition of more specialized programmable function blocks like
ALUs, block RAM, multiplexers, DSP-48, and microprocessors.
Application
Different Types of FPGA
Different Types of FPGA
Logic Synthesis
2 LEVEL LOGIC OPTIMIZATION
Multi level Optimization Technique
Library optimization
Logic Implementation By Macros
Compiler Directives

 They allow for macros, inclusion of files, and timescale-related


parameters for simulation.
 All compiler directives are preceded by the ‘`’ (accent grave)
character
 The `define compiler directive can also be used to substitute a
number by a macro name
 It allows for deciding bus-width, specific delay values, etc., at
compilation time
 A wide range of timescales as well as precision levels are available for selection during
simulation
`timescale
 The `timescale compiler directive allows the time scale to be specified for the design.
 When a `timescale directive is encountered in a file, the same is valid for all
subsequent modules within the file
timescale 1 ms/100 μs
implies that in the following design all the
time values specified are in ms and they
have a precision of 100 μs.
Thus 3, 3.0, 3.022 are all interpreted as 3
ms;
3.1, 3.12,3.199 are all
interpreted as 3.1 ms;
0.1, 0.12 are interpreted as
100 μs.

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