Verilog HDL

Introduction
• Verilog HDL is a general purpose HDL that is easy
to learn and use.
• Syntax is similar to the C programming language.
• It allows different levels of abstraction to be
mixed in the same model.(switch, gates, RTL or
behavioral code)
• Most popular logic synthesis tools support
verilog HDL.
• This is a case sensitive language.
• It has built in gate level and switch level
primitives.
 VHDL & VERILOG

VHDL Verilog HDL

Origin (start) US Department of Defense Cadence Design Systems (1985)
(1987)
Domain Public (IEEE Standard 1076) Public (IEEE Standard 1364)
Levels of modeling (mixing system, functional, structural, functional, structural, RTL, gate,
allowed?) RTL, gate (yes) switching (yes)
Looks like Ada c
Level of complexity difficult average
Easy to read no average
Predefined features poor good
Designer friendly no yes
Designers Acceptance widely used widely used
Tool independent yes more or less
Straightforward hardware not really partially
meaning
Clock model asynchronous, multi- phase, asynchronous, multi- phase,
multiple clocks multiple clocks
Timing properties sequential and concurrent sequential and concurrent
Finite state machine implicit, verbose implicit, verbose
Semantics for simulation (speed) yes (average) yes (fast)
Semantics for synthesis no no
 Module – Basic Building Block
Module <module-name> (<module_terminal_list);
…..
<module internals>
…..
…..
endmodule
--module-name🡪identifier
--module_terminal_list🡪input & output terminals
Module
 Ports
• Ports provide the interface by which a module can communicate
with its environment.
• List of Ports

• All port declarations are implicitly declared as wire.

• Input or inout ports are normally declared as wires.
• However if output ports hold their value, they must be declared
as reg.
• Input and inout cannot be declared as reg.
Port Connection Rules
 Basic Concepts
• Lexical Conventions – stream of tokens
• Tokens can be comments, delimiters, strings, numbers, identifiers
and keywords.
• Whitespace
\b – blank space
\t – tabs
\n – newlines
• Comments
// - single line
/*…*/ - Multiple line
• Operators
Unary operators - ~
Binary operators - &&
Ternary operators - ?
 Basic Concepts
• Number Specification
sized numbers:
represented as <size>’<base format><number>
<size> - is written only in decimal and specifies the no of bits in
the number.
‘d or ‘D – Decimal
‘h or ‘H – Hexadecimal
‘b or ‘B – Binary
‘o or ‘O – Octal
Egs. 4’b1111 //4-bit binary number
12’habc //12-bit hexadecimal number
16’d255 //16-bit decimal number
 Basic Concepts
• Unsized numbers
--Numbers that are specified without a base
format are decimal numbers by default
-- Default bit size – 32 bit
• X or Z Values
-- Unknown value – x
-- High Impedance – z
• Negative numbers
-6’d3 // 8-bit negative no stores as 2’s complement of 3
• Underscore & Question Marks
“_” is allowed anywhere in a no except the first character.
eg: 12’b1111_0000_1010 //for readability
“?” is alternative for z in the context of numbers.
eg: 4’b10?? // equivalent of a 4’b10zz
 Basic Concepts
• Strings
“Hello World” //is a string
• Identifiers and Keywords
-- Identifiers are made up of alphanumeric
characters, an underscore, $ sign.
-- Identifiers are case sensitive
-- Must start with alphabet or an underscore
-- Must not start with a digit or $ sign
 HALF ADDER using Dataflow Modeling

module ha_df(sum,carry,a,b);
input a,b;
output sum,carry;
assign sum=a^b;
assign carry=a&b;
endmodule
Half Adder – Structural Modeling
Full Adder – Structural Modeling
 Full Adder using Half Adder

module fa_ha(sum,carryout,p,q,carryin);
input p,q,carryin;
output sum,carryout;
wire s,co1,co2;
ha_df ha1(s,co1,p,q);
ha_df ha2(sum,co2,s,carryin);
or o1(carryout,co1,co2);
endmodule
4-bit Ripple Carry Adder using FA
Operator Types & Symbols
Operator Types & Symbols
 Arithmetic Operators
• Binary Operators
- multiply(*),divide(/),add(+),subtract(-),
power(**)and modulus(%)
• Unary Operators
- + and – can also work as unary operators.
eg -4 –negative 4
+5 –positive 5
 Logical Operators

•If any operand is not equal to zero, it is equivalent to a logical 1. If it is equivalent

To zero, it is equivalent to logical 0.
•If any operand bit is x or z, it is equivalent to x and is treated as false condition.
 Relational Operators
// A=4, B=3
//X=4’b1010 Y=4’b1101 Z=4’b1xxx
A<=B // logical 0
A>B // logical 1
Y>=X // logical 1
Y<Z // X
Equality Operators
Bitwise Operators
Reduction & Shift Operators
Concatenation & Replication Operators
 Conditional Operator
Usage:
Condition_exp ? True_exp : false_exp ;
2:1 Multiplexer Pgm using conditional operator
4:1 Mux using Conditional Operator
 Conditional Statements in Behavioral
Modeling – IF statement
• If
1. if (<expression>) true-stmt;
2. if(<expression>)true-stmt; else false-stmt;
3. if(<expression>)true-stmt1
else if (<expression>) true-stmt2;
else if (<expression>) true-stmt3;
else default-stmt;
• Multiple statements can be grouped using begin
and end.
 case statement
• Keywords are case, endcase and default.
• Syntax:
case (expression)
alternative1: statement 1;
alternative2: statement 2;
alternative3: statement 3;
…………….
default: default-statement;
endcase
• Default statement is optional
• Case statements can be nested
Half Adder using if statement
4:1 MUX using case
1:4 Demux using case
JK Flip Flop
 Structured Procedures
• Initial statement
--initial block starts at time 0, executes exactly once
during a simulation
--if there are multiple blocks, each block starts to
execute concurrently at time 0
--multiple statements can be grouped using begin
and end
--initial blocks are used for initialization, monitoring,
waveforms and other processes that must be
executed only once during the entire simulation run
 Structured Procedures
• Always statement
--starts at time 0 and executes the statements
in the always block continuously in a looping
fashion
--used to model a block of activity that is
repeated continuously in a digital circuit
 Example for initial and always
module clk_gen(output reg clock);
//initialize clock at time zero
initial
clock=1’b0;
//toggle clock every half-cycle(time period=20)
always
#10 clock = ~clock;
initial
#1000 $finish;
endmodule
 Procedural Assignments
• Procedural assignments update values of
integer, real or time variables
• The value placed on a variable will remain
unchanged until another procedural
assignment updates the variable with a
different value.
• Two types of procedural assignments are
- blocking assignments
- nonblocking assignments
 Blocking Assignments
• Blocking assignment statements are executed in the order they are specified
in a sequential block
Blocking Assignments
Nonblocking Assignments
Nonblocking Assignments
Nonblocking Assignments to Eliminate Race
Condition
Implementing Nonblocking using blocking
assignments
Tasks and Functions
Task Declaration and Invocation
Function Declaration and Invocation
Task - Example
Task
Function Example
Function
 Compiler Directives
• `define – (Similar to #define in C) used to define global
parameter
• Example:
`define BUS_WIDTH 16
reg [ `BUS_WIDTH - 1 : 0 ] System_Bus;
• `undef – Removes the previously defined directive
• Example:
`define BUS_WIDTH 16
…
reg [ `BUS_WIDTH - 1 : 0 ] System_Bus;
…
`undef BUS_WIDTH
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 Compiler Directives (cont.)
• `include – used to include another file
• Example
`include “./fulladder.v”

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 System Tasks
• Display tasks
– $display : Displays the entire list at the time when
statement is encountered
– $monitor : Whenever there is a change in any argument,
displays the entire list at end of time step
• Simulation Control Task
– $finish : makes the simulator to exit
– $stop : suspends the simulation

• Time
– $time: gives the simulation
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 Loop Statements
• Loop Statements
– Repeat
– While
– For

• Repeat Loop
– Example:
repeat (Count)
sum = sum + 5;
– If condition is a x or z it is treated as 0
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 Loop Statements (cont.)
• While Loop
– Example:
while (Count < 10) begin
sum = sum + 5;
Count = Count +1;
end
– If condition is a x or z it is treated as 0

• For Loop
– Example:
for (Count = 0; Count < 10; Count = Count + 1) begin
sum = sum + 5;
end
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 Loop Statements (cont.)
Forever Loop:

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 Data Types
• Net Types: Physical Connection between structural
elements
• Register Type: Represents an abstract storage element.
• Default Values
– Net Types : z
– Register Type : x

• Net Types: wire, tri, wor, trior, wand, triand, supply0,

supply1
• Register Types : reg, integer, time, real, realtime
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 Data Types
• Net Type: Wire
wire [ msb : lsb ] wire1, wire2, …
– Example
wire Reset; // A 1-bit wire
wire [6:0] Clear; // A 7-bit wire
• Register Type: Reg
reg [ msb : lsb ] reg1, reg2, …
– Example
reg [ 3: 0 ] cla; // A 4-bit register
reg cla; // A 1-bit register
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 Restrictions on Data Types
• Data Flow and Structural Modeling
– Can use only wire data type
– Cannot use reg data type

• Behavioral Modeling
– Can use only reg data type (within initial and
always constructs)
– Cannot use wire data type

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 Memories
• An array of registers
reg [ msb : lsb ] memory1 [ upper : lower ];

• Example
reg [ 0 : 3 ] mem [ 0 : 63 ];
// An array of 64 4-bit registers
reg mem [ 0 : 4 ];
// An array of 5 1-bit registers

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 Switch Level Modeling

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 Switch Level Modeling

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 Switch Level Modeling

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 Switch Level Modeling

module my_nor(out,a,b);
output out;
Input a,b;
supply1 vdd;
supply0 gnd;
wire c;
pmos p1(c,vdd,b);
pmos p2(out,c,a);
nmos n1(out,gnd,a);
nmos n2(out,gnd,b);
endmodule

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 Switch Level Modeling

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 Switch Level Modeling

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