SEMINAR ON

ARM PROCESSOR

CONTENT
        

Introduction. History Of ARM Processor. Two computer architectures. The ARM Architecture. ARM Architecture features. Improved memory management. Advantages. Applications. Conclusion.

INTRODUCTION

History of RISC computers



First commercial RISC in 1985 by Acorn First low-cost RISC-powered PC in 1987 by Acorn ARM (joint venture of Acorn+Apple+VLSI) was established in Nov 1990 StrongARM (joint venture of ARM+Digital) established in 1998 Intel bought the license for StrongARM from ARM

Two Computer Architecture

RISC (Reduced Instruction Set Computing). CISC (Complex Instruction Set Computing).

Comparison between RISC & CISC

Sr. No 1 2 3 4 5 6 7 8 RISC
Simple instructions taking 1 cycle. Only LOADS/STORES reference memory. Highly pipelined Instructions executed by the hardware. Fixed format instructions. Few instructions and modes. Complexity is in the compiler. Multiple register sets.

CISC
Complex instructions taking multiple cycles. Any instruction may reference memory. Not pipelined or less pipelined. Instructions interpreted by the microprogram. Variable format instructions. Many instructions and modes. Complexity is in the microprogram. Single register set.

ARM11 Family & Features

Core Arch Implementation Feature cache (I/D)/M MU Typical MIPS @MHz In Application

ARMv6

ARM1136(f)-S

SMID,Jazelle DBX,(VFP), 8-Stage pipeline SMID, Thumb-2, (VFP), 9-Stage Pipeline SMID Jazelle DBX, (VFP)

Variable, MMU

?? @53266M11z (I,MX31SoC)

Nokia N95, Nokia N93, Zune,Nokia N800,Texas Instruments OMPA2

ARM11

ARMv6T2

ARM1156T2(F)-S

Variable, MMU

ARMv6Kz

ARM11JZ(F)-S

Variable, MMU+T rustZone

ARMv6k

ARM11 MPCore

1-4 Core SMP, SMID, Jazelle, DBX,(VFP)

Variable, MMU

THE ARM ARCHITECTURE

ARM instruction set architecture (Version1)
This version was implemented by ARM 1 and was never used in a commercial product. It had only 26-bit address space and is now obsolete.

It contained:
    

The basic data processing instructions (not including multiplies) Byte, word, and multi-word LOAD / STORE instructions Branch instructions, including a branch-and-link instruction designed for subroutine calls A software interrupt instruction, for use in making Operating System calls

ARM instruction set architecture (Version2)

This version extended the Version 1 architecture by adding:
   

Multiply and multiply-accumulate instructions Coprocessor support Two more banked registers in fast interrupt mode Atomic load-and-store instructions called SWP and SWPB ( in a slightly variant version called version 2a)

Version 2 and 2a still only had a 26-bit address space and are now obsolete

ARM instruction set architecture (Version3)

   

Extended the addressing range to 32-bits Program Status information which was stored in R15 previously is now been stored in the Current Program status Register (CPSR) and Saved Program Status Registers (SPSRs) to preserve the CPSR contents when an exception occurs.

The following changes occurred to the instruction set: - two instructions (MRS and MSR) were added to allow the new CPSR and SPSRs to be accessed - the functionality of instructions previously used to return from exceptions was modified to allow them to continue to be used for that purpose Two new processor modes were added to use Data Abort, Prefetch Abort and undefined Instructions exceptions effectively in Operating System codes


ARM instruction set architecture (Version4)

This version added the following to the architecture Version 3:
   

Halfword load/store instructions Instructions to load and sign-extend bytes and halfwords In T variants , an instruction to transfer to Thumb state A new privileged processor mode that uses the User mode registers.

Version 4 also made it clearer which instructions should cause the undefined Instruction exception to be taken.

ARM instruction set architecture (Version5)

This version added some new instructions and modified the definitions of some of the instructions of Version 4 to:
 

Improve the efficiency of ARM/Thumb ineterworking in T variants Allow the same code generation techniques to be used for non-T variants as for T variants

Version 5 also:
    

Adds a count leading zeros instruction, which (among other things) allows more efficient integer divide and interrupt prioritization routine Adds a software breakpoint instruction Adds more instruction options for coprocessors designers Tightens the definitions of how flags are set by multiply instructions

ARM Instruction Set Architecture (Version6)

Key ARMv6 Improvements:1. Memory Management 2. Multiprocessing 3.Multimedia Support 4. Data Handling 5.Exceptions and Interrupts

The Thumb Instruction Set (T Variants)

Thumb Instruction Set are:
  

Introduced with architecture version 4 Re-encoded subset of ARM instruction set Half the size of ARM instructions (16-bits compared with 32), hence greater code density

Limitations:
 

Thumb code usually uses more instructions for the same job, so ARM code is usually best for maximizing the performance of time-critical code The Thumb instruction set does not include some instructions that are needed for exception handling, so ARM code needs to be used for at least top-level exception handlers (Due to this reason Thumb Instruction is used in conjunction with a suitable ARM instruction set)

ARM Architecture Features

The typical RISC Features:
     

A large uniform register file A load/store architecture, where data-processing operations operate only on register contents, not directly on memory contents Simple addressing modes, with all load/store addresses being determined from register contents and instruction fields only Uniform and fixed-length instructions fields, to simplify instruction decode

ARM Architecture Features (Continued)

Additionally, ARM instruction gives:


Control over both the ALU and shifter in every data processing instruction to maximize the use of an ALU and a shifter Auto-increment and auto-decrement addressing modes to optimize program loops Load and Store multiple instructions to maximize data throughput Conditional execution of all instructions to maximize execution throughput.

   

These enhancements to a basic RISC architecture allow ARM processor to achieve a good balance of high performance, low code size, low power consumption and low silicon area

Improved Memory Management

Classification of ARM Instruction set

1.

Branch instructions Data processing instructions Status register transfer instructions Load and store instructions Coprocessor instructions Exceptions-generating instructions

2.

3.

4.

5.

6.

APPLICATIOS

Processors for Consumer and Wireless Digital TV, DVD, PVR, Set-top box, games, Digital camera Automotive, Data Storage, Imaging and Embedded Control Processors for Network Infrastructure Computer :PDA, Printer, Data Storage

CONCLUSION

ARM partners will be able to differentiate and optimize ARM11 cores for power and performance, exploiting the characteristics of their own process technologies. The new microarchitecture is targeted at next-generation highend portable and wireless applications, consumer, networking, and automotive applications. There are many features that will also make ARM11 processors highly suited to high-end embedded realtimeapplications, such as future networking and in-home entertainment products now require

Thank You !