Module-2

Machine Instructions and Programs cntd..

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 Memory locations and
Address
 Number and character operands, as well as instructions, are

stored in the memory of a computer.

 We will now consider how the memory is organized. The memory

consists of many millions of storage cells, each of which can store a

bit of information having the value 0 or 1.
 Because a single bit represents a very small amount of information ,

bits are not handled individually. The usual approach is to deal with
them in groups of fixed size.
 For this purpose, the memory is organized so that a group of n bits

can be stored or retrieved in a single basic operation.

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 Each group of n bits is referred to as a word of

information, and n is called word length.

 The memory of a computer can be schematically

represented as a collection of words.

 If the word length of a computer is 32 bits, a single

word can store a 32- bit 2’s complement number

or four ASCII characters, each occupying 8 bits .
 A unit of 8 bits is called a byte.

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5 Friday, December 13, 20
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Byte addressability:
•We now have three basic information quantities to deal

with the bit, byte, and word.

•A byte is always 8 bits, but the word length typically

ranges from 16 to 64 bits.

•It is impractical to assign different address to

individual bit locations in the memory.

•The most practical assignment is to have successive

address refer to successive byte locations memory. this

is called BYTE ADDRESSABLE memory.
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 Big-Endian and Little –Endian assignments
• There are two ways that byte address can be assigned across

words as shown in the figure.

Big-Endian:
• The name big- endian is used when lower byte addresses are

used for the more significant bytes(left most bytes) of the

word.
Little- Endian:
• The name little-endian is used for the opposite ordering, where

the lower byte addresses are used for the less significant
bytes(the right most bytes)of the word.

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 In both cases, byte addresses 0,4,8……. are taken
as the addresses of successive words in the
memory.

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Word Alignment:
• In case of a 32- bit word, boundaries occur at
addresses 0,4,8,….. As shown in the figure.
• Thus , we say that the word locations have aligned

addresses.
• if the word length is 16(2 bytes), aligned words begin

at byte addresses 0,2,4,…..for a word length of 64(8

bytes), aligned words begin at addresses 0,8,16,……

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Each group of n bits is referred to as a word of

information, and n is called word length.

The memory of a computer can be
schematically represented as a collection of
words.

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 Accessing numbers, characters ,
and character strings
• A number usually occupies one word. It can be accessed in

the memory by specifying its word address.

• Similarly, individual characters can be accessed by their byte

address.
• In many applications, it is necessary to handle character

strings of variable length.

• The beginning of the string is indicated by giving the address

of the byte containing its first character. Successive byte

locations contain successive characters of the string.

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 There are two ways to indicate the length of

the string:

1) A special character with the meaning “end of

the string “ can be used as the last character in the
string.

2)A processor register can contain a number

indicating the length of the string in the bytes.

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 Memory operations
• Both program instructions and data operands are
stored in the memory.
• To execute an instruction, the processor has to
fetch that instruction from memory.
• The result of the operation may also be copied to
the memory.
• Thus, two basic operations are performed with the
memory.
1. Load(read or fetch)
2. store (write)

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 Load operation
• The load operation transfers a copy of the contents
of a specific memory location to the processor. The
memory contents remain unchanged.
the steps are
1. processor sends the address of the desired
memory location.
2. processor issues a read control signal to memory
to request the data .
3. Memory sends the data to the processor.
4. Data gets stored in processor register.

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 Store(Write) operation
• The store operation transfers an item of
information from the processor to a specific
memory location, destroying the former contents
of that location.
the steps are
1. Processor sends the address of the memory
location where it wants to store data.
2. A write signal is issued by the processor.
3. The content of the processor register is written
into the specified memory location.

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 Instructions & instruction
sequencing
• A computer performs its task according to the
program stored in memory.
• A program is a collection of instructions which tell
the processor to perform a basic operation like
addition, reading a character from keyword.
• A computer should have instructions to perform at
least four types of operations listed below.
1. data transfer between memory and processor
registers.
2. Arithmetic and logic operations on data.
3. program sequencing and control.
4. I/O transfers.
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 To illustrate the operations, we need to know how to
represent the operations and operands for an
instruction.
 In this section two types of notations.
Register Transfer Notation(RTN):
 In this notation, we identify a memory location by a
symbolic name in the upper case letters, the name
indicates its address. For example, LOCA, A, VAR2;
processor register names may be R0, R5; and I/O
register names may be DATAIN, DATAOUT.

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 R1 [LOCA]
• The contents of a location are denoted by placing
square brackets around the name of the location.
• Thus the expression means that the contents of
memory location LOCA are transferred into processor
register R1.
• As another example, consider the operation that
adds the contents of the register R1and R2, and then
places their sum into register R3. this action is
indicated as
R3 [R1]+[R2]
This type of notation is known as register transfer
notation.
Note that the Right- hand side of an RTN expression
always denotes a value and the Left-hand side is the
18 name of the location where the value is to December
Friday, be placed,
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overwriting the old contents of that location.
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 Assembly language notation:
 We need an another type of notation to represent
machine instructions and programs.
 For this, we use an assembly language format.
 For example, an instruction that causes the transfer
from memory location LOCA to processor register R1,
is specified by the statement.
MOV LOCA, R1
The contents of LOCA are unchanged by the execution
of this instruction, but the old contents of register R1
are overwritten.
The second example of adding two numbers contained
in the processor registers R1 and R2 and placing
their sum in R3 can be specified by the assembly
language statement .
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December 13, 20
 Basic instruction types
A statement like C = A+B in a high – level
language program informs the computer to add
the values of the two variables called A and B and
assign the sum to a third variable called C. when
the program containing this statement is
compiled, each variable is assigned a different
address in memory. The contents of these
locations represents the values of three variables.
Hence, the above high- level language statement
requires the action
C  [A] + [B]
To carry out this kind of operation, assembly
language provides three types of instruction
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 Three address instruction:
• The instruction has the format
operation Source1, source2, Destination
Using this format the above operation can be
completed using a single machine instruction as
Add A,B,C
A and B are called source operands, C is the
destination operand and Add is the operation to be
performed. This type of instruction has the
disadvantage the instruction code will be too large
to fit in one word location in memory.

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 • If k bits are needed to specify the memory address
of each operand, the encoded form of the above
instruction must contain 3k bits for addressing
purposes in addition to the bits needed to denote
the Add instruction.
Two address instruction:
• The general format is
operation Source, Destination
An add instruction of this type is
Add A,B
Which performs the operation B  [A] +[B]. when
the sum is calculated, the result is sent to the
memory and stored in location B, replacing the
original contents of this location. This means that
operand B is both source and destination.
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 • A single two – address instruction cannot be used
to solve our original problem, which is to add the
contents of locations A and B, without destroying
either of them, and to place the sum in location C.
• This problem can be solved by using another two
address instruction that copies the contents of one
memory location into another.
such an instruction is Move B,C which
performs the operation C [B]. Leaving the
contents of location unchanged.
• The operation C [A] +[B] can now be performed
by the two – instruction sequence.
Move B,C
Add A,C

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 • In all the instructions given above, the source
operands are specified first, followed the
destination. This order is used in the assembly
language expressions for machine instructions in
many computers. But there are also many
computers in which the order of the source and
destination operands are reversed.
• We have discussed three and two address
instructions . But even two address instructions will
not normally fit into one word.
• Another possibility is to have machine instructions
that specify only one memory operand. when a
second operand is needed, as in the case of an add
instruction, is understood implicitly to be in a
unique location.
• A processor register usually called the accumulator
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may be used for this purpose. 24
 One –Address instruction:
• The general format is
operation source/destination
e.g. Add A
This instruction adds the contents of the memory
location A to the contents of the accumulator
register and place the sum back into the
accumulator.
Load A
The load instruction copies the contents of the
memory location A into the accumulator.
Store A
The store instruction copies the contents of the
accumulator into memory location A.
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  Using one address- instructions, the operation C
 [A]+[B] can be performed by executing the
sequence of instructions.
Load A
Add B
Store C
 Note that the operand specified in the instruction
may be source or a destination, depending on the
instruction.

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 In processors, where arithmetic operations are
allowed only on operands that are in the processor
registers , the C= A+B task can be performed by
the instruction sequence
move A, Ri
move B, Rj
Add Ri, Rj
move Rj, c

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 • In processors where one operand may be in the
memory but the other must be in a register, an
instruction an instruction sequence for the
required task would be
Move A, Ri
Add B, Ri
move Ri, C
• We have discussed three- two-, and one- address
instructions. It is also possible to use instructions
in which the locations of all operands are defined
implicitly. such instructions are found in machines
that store operands in a structure called a
pushdown stack.

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 Addressing modes
 The different ways in which the location of an operand
is specified in an instruction are referred to as
addressing modes.
 We can access an operand by specifying the name of
the register or the address of the memory
location where the operand is located.
Register Mode:
The operand is the contents of a processor register, the
name(address) of the register is given in the
instruction.
e.g. MOV R1,R2
The instruction copies the contents of register R1 to
register R2.
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Absolute mode:

The operand is in a memory location; the address of

this location is given explicitly in the instruction.
(In some assembly languages, this mode is called
direct).
The instruction uses two modes.
E.g. MOV LOCA,R2
Processor registers are used as temporary storage
locations where the data in a register are
accessed using register mode.

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Immediate mode:

• The operand is given explicitly in the instruction.

e.g. MOV 200immediate,R0
 The instruction places the value 200 in the register R0.
 The immediate mode is only used to specify the value of a
source operand. Using a subscript to denote the immediate
mode is not appropriate in assembly languages.
 A common convention is to use the sharp sign (#) in front of
the value to indicate that this value is to be used as an
immediate operand.
Hence we write the instruction above in the form
MOV #200,R0

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Indirect mode:
 In this addressing mode, the instruction does not give the

operand or its address explicitly. instead it provides information

from which the memory address of the operand can be
determined. we refer to this address as the effective
address(EA) of the operand.
 The effective address of an operand is the contents of register

or memory location whose address appears in the instruction.

 To execute the add instruction in the figure(A) the processor

uses the value B, which is in the register R1, as the effective

address of the operand. the value read is desired operand,
which the processor adds to the contents or register R0.
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33 Friday, December 13, 20
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 Indirect addressing through a memory location is also possible as

shown in the figure(b). In this case processor first reads the contents of
memory location A, then requests a second read operation using the
value B as an address to obtain the operand.
 The register or memory location that contains the address of an

operand is called a pointer.

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35 Friday, December 13, 20
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 Let us now return to the program of adding list of numbers.
 Indirect addressing can be used to access successive numbers
in the list, resulting in the program shown in the figure.
 Register R2 is used as a pointer to the numbers in the list, and
the operands are accessed indirectly through R2.

 The initialization section of the program loads the counter value

‘n’ from memory location ‘N’ into R1 and uses the immediate
addressing mode to place the address value NUM1, which is the
address of first number in the list into R2.
 Then it clears R0 to 0.
 The first through the loop, the instruction
ADD (R2),R0
Fetches the operand at location NUM1 and adds it to R0.the
second ADD instruction adds 4 to the contents of the pointer
R2,so that it will contain the address value NUM2.

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Index mode :
 The effective address of the operand is generated by
adding a constant value to the contents of a
register.
 The register used may be either a special register
provided for this purpose, or more commonly, it may
be any one of a set of general-purpose registers in the
processor.
 In either case, it is referred to as an index register.
 We indicate the index mode symbolically as
X(Ri)
X denotes the constant value in the instruction, Ri is
name of the register involved.
Effective address of the operand is given by
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38 Friday, December 13, 20
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39 Friday, December 13, 20
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 Figure illustrates two ways of using the index mode.
 In figure A the index register R1, contains the address
of a memory location and the value X defines an
offset(also called displacement) from this address to
the location where the operand is found.
 An alternative use is illustrated in figure B. Here, the
constant X corresponds to a memory address, and the
contents of the index register define the offset to the
operand.
 In either case, the effective address is the sum of the
two values, one is given explicitly in instruction and
the other is stored in a register.

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 Base with Index Mode
 In this addressing mode Effective Address is the
sum of two registers.
Syntax:
(Ri,Rj)

Effective Address:

EA= [Ri]+[Rj]

The first register is called Index Register.

The second register is called Base Register.

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 Base with Index and Offset
 In this addressing mode effective address is the
sum of the constant(X) and the contents of the two
registers.

Syntax:
X(Ri,Rj)

EA=[Ri]+[Rj]+X

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Relative Addressing:
 We have discussed the index mode using general-purpose
register.
 A useful version of this obtained if program counter(PC) is used
instead of a general purpose register.
 Then X(PC) can be used to address a memory location that is X
bytes away from the location pointed by the program counter.
EA=[PC]+X
The effective address is determined by the index mode using the
program counter in the place of the general purpose register.
Its common use is to specify the target address in branch
instructions. An instruction such as
Branch>0 Loop
Causes program execution to go to the branch target location
identified by the name LOOP if the branch condition is satisfied.
this location can be computed by specifying it as an offset from
the current value of the program counter
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 Additional Modes
 So far we have discussed the six basic addressing modes- register,
absolute, immediate, index, indirect and relative.
 Many computers provide two additional modes:

1) Autoincrement Mode
2) Autodecrement Mode

Autoincrement mode:
 The effective address of an operand is contents of register specified in
the instruction. After accessing the operand, the contents of the register
are automatically incremented to point to the next item in the list.
 We denote autoincrement mode by putting the specified register in
parentheses, to show that contents of register are used as the effective
address.

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 The autoincrement mode is written as
(Ri)+
Autodecrement mode:

 The contents of a register specified in the instruction are first

automatically decremented and are then used as the
effective address of the operand.
 We denote the autodecrement mode by putting the specified
register in parentheses, preceded by a minus sign to indicate
that the contents of the register are to be decremented before
being used as the effective address. Thus we write
-(Ri)

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46 Friday, December 13, 20
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 STACK
 Data operated on by a program can be organized in a
variety of ways.
 Now, we consider the important data structure known
as STACK.
 A stack is a list of data elements usually words or
bytes with the accessing restriction that elements can
be added or removed at one end of the list only, this
end is called TOP of the STACK, and the other end is
called the bottom.
 The structure sometimes referred to as a pushdown
stack or last –in first –out(LIFO). That is the last data
item placed on the stack is the first one removed
when retrieval begins.

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PUSH:
 Placing a new item on the stack.
POP:
 Removing the top item from the stack.

 Assume that the first element is placed in location bottom, and

when new elements are pushed onto the stack, they are placed
in successively lower address locations. We use a stack that
grows in the direction of decreasing memory addresses in our
discussion, because this is common practice.

 The figure shows a stack of data items in the memory of a

computer, it contains numerical values, with 43 at the bottom
and -28 at the top.
 A processor register is used to keep track of the address of the
element of the stack that is at the top at any given time. this
register is called the STACK POINTER(SP).

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49 Friday, December 13, 20
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 If we assume a byte addressable memory with 32-bit word length
the push operation can be implemented as

Subtract #4,SP
Move NEWITEM,(SP)

These two instructions move the word from location NEWITEM onto
the top of the STACK decrementing the stack pointer before the
move.

The POP operation can be implemented as

Move (SP), ITEM
Add #4,SP
These two instructions move the top value from the stack into the
location ITEM and then increment the stack pointer by 4 so that it
points to the new top element. The figure shows the effect of the
each of these operations on the stack.
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51 Friday, December 13, 20
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 If the processor has the autoincrement and autodecrement

addressing modes the push operation can be performed by the

single instruction

MOVE NEWITEM, -(SP)

And pop operation can be performed by

MOVE (SP)+, ITEM

 When a stack used in a program, it is usually allocated a fixed

amount of space in the memory .

 In this case we must avoid pushing an item onto the stack

when the stack has reached its maximum size.

 Also, we must avoid attempting to POP an item off an empty

stack, which could result from a programming error.

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 Suppose that a stack runs from location 2000(bottom) .

 The stack pointer is loaded initially with the address value 2004.

recall that SP is decremented by 4 before new item pushed on the

stack. Hence an initial value of 2004 means that the first item
pushed onto the stack will be at location 2000.
 To prevent either pushing an item on a full stack or popping

an item off an empty stack the single instruction push and pop
operations can be replaced by the instruction sequences shown in
the figure.

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 SAFE PUSH

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 SAFEPOP

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 SUBROUTINES
 In a given program, it is often necessary to perform a particular

subtask many times.

 A subroutine is a group of instructions, performs a particular

subtask which is executed number of times. It is written

separately.
 The processor executes this subroutine by transferring the
program control to the subroutine program.
 After completion of subroutine program execution, the program

control is returned back to the main program.

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57 Friday, December 13, 20
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CALL Instruction:

The call instruction performs the following operations

 Store the contents of the Program counter(PC) in the link register.

 Branch to the target address specified by the instruction.

RETURN Instruction:
 Loads the program counter(PC) with the contents of link register

and branch to that address.

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 Subroutine Nesting
 When one subroutine calls another subroutine to complete a
particular task, the operation is called NESTING.

Calling program SUB1 SUB2

1 1 1
2 2 2
3 3 3
CALL SUB1 CALL SUB2 4
5 5 5
6 RET
RET

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 In this case, the return address(RA) of the second call is also

stored in the link register, destroying its previous contents.

 Hence it is essential to save the contents of the link register in

some other location before calling another subroutine, otherwise

the return address of the first subroutine will be lost.

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 Parameter Passing
 When calling a subroutine, a program must provide to the

subroutine the parameters , that is operands or their addresses,

to be used in the computation.
 Later the subroutine returns other parameters, in this case the

results of the computation.

 This exchange of information between a calling program and a

subroutine is referred to as parameters passing.

 Parameters passing may be accomplished in several ways.

 The parameters may be placed in registers or in memory

locations, where they can be accessed by subroutine.
 Alternatively, the parameters may be placed on the processor
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 Passing Parameters Through
Registers.
 Passing parameters through registers is straight forward and

efficient.

 Figure shows how the program for adding a list of numbers can be

implemented as subroutine.

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63 Friday, December 13, 20
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 If many parameters are involved, there may not be

enough general-purpose registers available for

passing them to the subroutine.

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65 Friday, December 13, 20
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66 Friday, December 13, 20
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 The Stack Frame
During the execution of subroutine the stack contains the entries

that are needed by the subroutine .

These locations constitute a private work space for the subroutine,

created at the time the subroutine is entered and freed up when the
subroutine returns control to the calling program. Such a space is
called a stack frame.
If the subroutine requires more space for local memory variables,

they can also be allocated on the stack.

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 Input/Output Design

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Accessing I/O devices:
 A simple arrangement to connect I/O devices to a
computer is to use a single bus arrangement as
shown in the figure.
 The bus enables all the devices connected to it to
exchange information.
 Bus consists of three sets of lines used to carry
Address
Data
Control Signals.
 Each I/0 device is assigned a unique set of
addresses.

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  When the processor places a particular address on the
address lines, the device that recognizes this address
responds to the commands issued on the control lines.
 The processor requests either a read or a write operation,
and requested data are transferred over the data lines.
 When I/0 devices and the memory share the same address
space, the arrangement is called memory mapped I/0.
 With memory mapped I/O, any instruction that can access
memory can be used to transfer data to or from an I/)
device.

 For example if DATAIN is the address of the input buffer

associated with the keyboard, the instruction
MOVE DATAIN,R0
Reads the data from DATAIN and stores them into processor
register R0.

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  Similarly the instruction
MOVE R0,DATAOUT
sends the contents of register R0 to location
DATAOUT,
 Most computer systems use memory-mapped I/O.
 Some processors have special IN and OUT
instructions to perform I/O transfers.
 For example, processors in the INTEL family have
special I/O instructions.

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73 Friday, December 13, 20
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 I/O Interface For Input Device
The figure shows the hardware required to
connect an I/O device to the bus.
Address decoder:
The address decoder enables the device to
recognize its address on the address lines.
Data and Status registers:
The data register holds the data being
transferred to or from the processor
The status register contains information
relevant to the operation of the I/O device.

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 Control Circuits:
Control circuitry required to coordinate I/O
transfers.

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 INTERRUPTS
 In program controlled I/O technique, the processor initiates
the action by checking the status of the device by entering
into a wait loop.
 During this period, the processor is not performing any useful
computation.
 There are many situations where other tasks can be
performed while waiting for an I/O device to become ready.
 To allow this to happen, we can arrange for the I/O device to
alert the processor when it becomes ready.
 It can do so by sending a hardware signal called an
INTERRUPT to the processor.
 At least one of the bus control lines, called an INTERRUPT
REQUEST LINE is usually dedicated for this purpose.
 Using interrupts waiting periods can ideally be eliminated.

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 EXAMPLE:
 Consider the task that requires some computations to be
performed and the results to be printed on a line printer.
 Let the program consist of two routines, COMPUTE and
PRINT.
 Assume that COMPUTE produces a set of “N” lines of
output, to be printed by the PRINT routine.
 But the printer accepts only one line of text at a time.
 First COMPUTE routine is executed to produce the first “N”
lines of output.
 Then the PRINT routine is executed to send the first line of
text to the printer., at this time instead of waiting for the
line to be printed, the print routine may be temporarily
suspended and execution of the COMPUTE routine
continued.

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  whenever printer becomes ready, it alerts the
processor by sending an interrupt request signal.
 In response, the processor interrupts the
execution of the COMPUTE routine and transfers
control to the PRINT routine.
 The PRINT routine sends the second line to the
printer and is again suspended.
 Then the interrupted COMPUTE routine resumes at
the point of interruption.
 This process continues until all “N” lines have
been printed and the PRINT routine ends.

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79 Friday, December 13, 20
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  This figure depicts the concept of interrupts
 The routine executes in response to an interrupt request is
called the INTERRUPT –SERVICE ROUTINE.
 Assume that an interrupt request arrives during the
execution of instruction “i” in figure.
 The processor first completes the execution of instruction
“i”. Then it loads the program counter with the address of
the first instruction of the interrupt service routine.
 After the execution of the interrupt service routine, the
processor has to come to instruction “i+1”.
 Therefore when interrupt occurs, the current contents of
the PC, which point to the instruction “i+1” must be put in
temporary storage .
 A return from interrupt instruction at the end of the
interrupt-service routine reloads the PC from that
temporary storage location.

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  The processor must inform the device that its request has
been recognized so that it may remove its interrupt- request
signal.
 This may be accomplished by means of a special control
signal on the bus.
 An interrupt –Acknowledge signal used in some of the
interrupt schemes.
 So far, treatment of an interrupt-service routine is very
similar to that of a subroutine.
 A subroutine performs a function required by the program
from which it is called.
 Subroutine and calling program belong to the same task.
 But an ISR may not have anything in common with the
program being executed at the time interrupt request is
received.

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  In fact, the two programs often belong to different tasks.
 Therefore, before starting the execution of the interrupt
service routine, any information that may be altered during
the execution of the interrupted program is resumed.
 The task of saving and restoring information can be done
automatically by the processor or by program instructions.

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  Saving registers increases the delay between the time an
interrupt request is received and the start of execution of
the interrupt-service routine.
 This delay is called INTERRUPT LATENCY.
 In some earlier processors, particularly those with small
number of registers , all registers are saved automatically
by the processor at the time an interrupt request is
accepted.
 The data saved are restored to their respective registers as
part of the execution of the return from interrupt
instruction.
 Some computers provide two types of interrupts
1) one saves all register contents
2) the other does not.

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 Enabling And Disabling
Interrupts
 When an interrupt arrives the processor suspends the
execution of one program and begins the execution of
another program requested by an I/O device.
 Because interrupts can arrive at any time, they may alter
the sequence of events.
 Hence, the interruption of program execution must be
carefully controlled.
 A fundamental facility found in all computers is the ability
to enable and disable such interrupts.

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  There are many situations in which processor should ignore
interrupt requests.
 For these reasons, some means for enabling and disabling
interrupts must be available for programmer.
 A simple way is to provide machine instructions, such as
interrupt enable and interrupt disable, that performs these
functions.
 Let us consider in detail the specific case of a single interrupt
request from one device.
 When device activates the interrupt request signal, it keeps the
signal activated until it learns that the processor has accepted
its request.
 It is essential to ensure that this active request signal does not
lead to successive interruptions, causing system to enter an
infinite loop from which it cannot recover.
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  Several mechanisms are available to solve this problem.
 We will discuss three possibilities here.

First Possibility:
 The processor hardware ignores the interrupt-request line until
the execution of the first instruction of interrupt-service routine
has been completed.
 Then, by using interrupt disable instruction as the first
instruction in the interrupt-service routine.
 Typically the interrupt-enable instruction will be the last
instruction in the interrupt-service routine.

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 Second Possibility:
 The processor automatically disables the interrupts before
starting the execution of the ISR.
 Prior to disabling, the processor should save the contents of PC
and PROCESSOR STATUS REGISTER(PS) on the stack.
 The processor status register has one bit called interrupt-enable
whish will enable interrupts when set to 1.
 After saving the contents of the PS on the stack, the processor
clears the interrupt-enable bit in its PS register, thus disabling
further interrupts.
 When return from interrupt instruction is executed, the contents
of the PS are restored from the stack, setting the interrupt enable
bit back to 1, hence interrupts are again enabled.

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 Third Possibility:
 The processor has special interrupt request line for which the
interrupt-handling circuit responds only to the leading edge of
the signal.
 Such a line is said to be edge-triggered.
 In this case processor will receive only one request, regardless
of how long the line is activated.
 Hence there is no danger of multiple interruptions and no need
to explicitly disable interrupt requests from this line .

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 Let us summarize the sequence of events involved in handling an
interrupt request from a single device
Steps:
 The device raises an interrupt request.
 The processor interrupts the program currently being executed.
 Interrupts are disabled by changing the control bits in the PS.
 The device is informed that its request has been recognized, and
in response, it deactivates the interrupt- request signal.
 The action requested by the interrupt is performed by the
interrupt-service routine.
 Interrupts are enabled and execution of the interrupted program
is resumed.

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 Handling Multiple
Devices
 Let us consider the situation where a number of devices
capable of initiating interrupts are connected to the
processor.
 Because these devices are operationally independent, there
is no definite order in which they will generate interrupts.
 For example, device X may request an interrupt while an
interrupt caused by Y is being serviced or several devices
may request interrupts at exactly the same time.
 This gives rise to a number of questions.

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 How processor recognize the device
requesting an interrupt.
Given that different devices are likely to
require different interrupt-service routines,
how can processor obtain the starting address
of the appropriate routine in each case?
Should a device be allowed to interrupt the
processor while another interrupt is being
serviced?
How should two or more simultaneous
interrupt requests be handled?

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 Polling Technique
When a device raises an interrupt request, it sets to
1 one of the bits in its status register, which we call
the IRQ bit.
For example bits KIRQ and DIRQ are the interrupt
request bits for the keyboard and the display.
The first device encountered with its IRQ bit set is
the device that should be serviced.
The polling technique is easy to implement.
DISADVANTAGE:
Its main disadvantage is the time spent interrogating
the IRQ bits of all devices that may not be requesting
any service.
An alternative approach is to use vectored

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interrupts. Friday, December 13, 20
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 Vectored Interrupts
 To reduce the time involved in the polling process, a device
requesting an interrupt may identify itself directly to the
processor.
 Then, the processor can immediately start executing the
corresponding interrupt-service routine.
 A device requesting an interrupt can identify itself by sending
a special code to the processor over the bus.
 This enables the processor to identify individual devices even
if they share a single interrupt-request line.
 The code supplied by the device may represent the starting
address of the interrupt-service routine for that device.
 The code length is typically in the range of 4 to 8 bits.

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 The location pointed to by the interrupting
device is used to store the starting address of
the interrupt-service routine.
The processor reads this address, called the
Interrupt vector.
When a device sends an interrupt request, the
processor may not be ready to receive the
interrupt-vector code immediately.
The interrupting device must wait to put data
on the bus only when the processor is ready
to receive it.
When processor is ready to receive the
interrupt-vector code, it activates the
interrupt-acknowledge line, INTA.
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 INTERRUPT NESTING
we discussed that interrupts should be disabled during the
execution of an interrupt-service routine, to ensure that a
request from one device will not cause more than one
interruption.
The same arrangement is often used when several devices
are involved, in which case execution of a given interrupt-
service routine , once started always continues to
completion before the processor accepts an interrupt
request from a second device.
Interrupt service routines are typically short, and the delay
they may cause is acceptable for most simple devices.
For some devices, however a long delay in responding to
an interrupt request may cause errors.
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 Consider, for example a computer that keeps track of the
time of day using real-time clock.
This is a device that sends interrupt requests to the
processor at regular intervals.
For each of these requests, the processor executes a short
interrupt-service routine to increment a set of counters in
the memory that keep track of time in seconds, minutes
and so on.
It may be necessary to accept an interrupt request from the
clock during the execution of an interrupt-service routine
for another device.
This example suggests that I/O devices should be
organized in a priority structure.

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 An interrupt request from a high- priority device should be
accepted while the processor is servicing another request
from a lower –priority device.
A multi-level priority organization means that during
execution of an interrupt service routine, interrupt requests
will be accepted from some devices but not from others,
depending upon the devices' priority.
To implement this scheme, we can assign a priority level to
the processor that can be changed under program control.
The priority level of the processor is the priority of the
program that is currently being executed.
The processor accepts interrupts only from devices that
have priorities higher than its own.

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  At the time the execution of an interrupt–service routine for
some device is started , the priority of the processor is raised to
that of the device.
 This action disables interrupts from the devices at the same level
of priority or lower.
 The processor’s priority is usually encoded in a few bits of the
processor status word.
 It can be changed by program instructions, called privileged
instructions.
Supervisor mode:
 The processor is in the supervisor mode only when executing
operating system routines.
User mode:
 The processor is in the user mode only when executing
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  A multiple-priority scheme can be implemented easily by using
separate interrupt-request and interrupt-acknowledge lines for
each device as shown in the figure.
 Each of the interrupt request lines is assigned a different
priority level.
 Interrupt requests received over these lines are sent to a priority
arbitration circuit in the processor.
 A request is accepted only if it has a higher priority level than
that currently assigned to the processor.

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100 Friday, December 13, 20
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 Simultaneous Requests
When multiple requests are received over a single request
line at the same time.
The processor must have some means of deciding which
request to service first.
DAISY-CHAIN:
So, method called Daisy-chain is a commonly used
hardware arrangement for handling many requests over a
single interrupt-request line.
The structure shown in the figure.
In this method, priority is determined by the order in
which these devices are polled.
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  The interrupt request line is common to all devices.
 The interrupt-acknowledge line (INTA) is connected ina daisy-
chain fashion, such that INTA signal propagates serially
through devices.
 When several devices raise an interrupt request and the INTR
line is activated, the processor responds by setting the INTA
line to 1.
 This signal is received by device 1.
 Device 1 passes the signal on to device 2 only if it does not
require any service.
 If device 1 has pending request for interrupt, it blocks the
INTA signal and proceeds to put its identifying code on the
data lines.
 Therefore, in the daisy-chain arrangement, the device that is
electrically closest to the processor has the highest
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 END OF Module 2

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