8085 MICROPROCESSOR

CHAPTER 2
3160914 : M&M
BY : H V HIRVANIYA
Intel 8085 Microprocessor
 The 8085A is an 8- bit microprocessor suitable for a wide range of application.
 It is a 40-pin DIP (Dual in package) chip, based on NMOS technology.
 It contains approximately 6200 transistors on a 164 x 222 mil chip.
 It requires a single +5V supply between Vcc at pin no. 40 and Vss at pin no. 20.
Intel 8085 Microprocessor
Pin Configuration of Intel 8085A

 A15 – A8 at pin no. 28 to pin no. 21:

 The microprocessor can address directly 2^16 memory locations or 65536 memory
locations or 64k memory locations using 16- address lines (A15-A0).
 Pin no. 28 to pin no. 21 give us the higher order 8-bits of the address (A15-A8).
 These address lines are unidirectional, tri-state address lines.
Pin Configuration of Intel 8085A

 AD7–AD0 at pin no. 19 to pin no. 12:

 AD7–AD0 are used for dual purpose.
 It is time multiplexed lower 8-bit address bus (A7-A0) and 8-bit data bus (D7-D0).
 Because at the time when this chip was developed, the practical limit on the
numbers of pins was 40.
 The only solution was to multiplex part of the address bus with the data bus.
States for the Processor

 The microprocessor, being a logic circuit, shall move from one state to the other state
during it operation.
 There are ten (10) different possible states for the processor and the processor will be
in one of these states as long as the power is ON.
States for the Processor

1. RESET STATE:
 Whenever microprocessor is reset, it enters in reset state.
 The microprocessor can be in RESET state for an integral multiple of clock cycle.

2. WAIT STATE:
 It can be in this state for an integral number of clock cycles, the duration being
determined by an external content signal input marked READY.
States for the Processor

3. HOLD STATE:
 As long as HOLD signal is active, microprocessor is in HOLD state.
4. HALT STATE:
 Microprocessor enters in this state when an HALT instruction is executed by the
processor.
 It remains in this state till such time when an external signal dictated by the user
asked the microprocessor to perform further duties.
States for the Processor

5. The other states the microprocessor can be in are marked T1, T2, T3, T4, T5 & T6
state.
 Each of these states is of one clock period duration.
 During each of these predetermined timing slots microprocessor performs very well
defined activities.
Pin Configuration of Intel 8085A

 Pin no.19 to pin no.12 are used by the microprocessor to send lower order 8-bits of
the memory address during T1 timing plot of a machine cycle.
 Therefore, the same 8-pins are utilized as bi-directional data bus for data transfer
operation in the subsequent timing plots T2 & T3.
 Hence, these pins are designated as AD7 – AD0.
Pin Configuration of Intel 8085A

 These 8 lines are also tri-state lines. They will be tri-stated during T4, T5 & T6 states.
 They will also be restated during DMA operation, during RESET operation & when a
HALT instruction is executed.
 These lines will also be tri-stated for a very short duration of time (few neon seconds)
between T1 &T2 states.
Pin Configuration of Intel 8085A

 ALE at Pin No 30:

 Low-order 8-bits of the address appear on the AD bus during the first clock cycle i.e., T1
state of a machine cycle.
 It then becomes the data bus during the second and third clock cycles i.e., T2 and T3 states.
 ALE stands for address latch enable. It is used to distinguish whether the AD7 – AD0 bus
contains address bits A7 – A0 or data bits D7- D0.
Pin Configuration of Intel 8085A
 ALE at Pin No 30:
 It is a single pulse issued during every T1 state of the microprocessor:
Pin Configuration of Intel 8085A
 De-multiplexing of AD bus to Generate System Bus:
Pin Configuration of Intel 8085A

 RD & WR Control signals at pin no 32 and at pin no 31:

 The BDB at pin no 19 to 12 are used for bi-directional data transfer operation during T2 &
T3 states.
 When the BDB is inputting the information from the external world into the
microprocessor, we say that 𝜇
𝑝 is in READ mode and operation is READ operation.
 When the 𝑝is outputting 8-bit of information to the external world through BDB we say 𝑝
is in WRITE mode and operation is WRITE operation.
Pin Configuration of Intel 8085A
Pin Configuration of Intel 8085A

 RD & WR Control signals at pin no 32 and at pin no 31:

 During WRITE operation, 𝑝first send the desired address on the address bus during T1 state,
thereafter it places the desired data on BDB which is now in input mode and then issues a
control signal, W R .
 A low level on W R indicates that the data on data bus is to be written in to the selected
memory location or I/O device. Data is setup at the trailing edge. It is for the user to take
appropriate action externally by the interfacing circuitry so that the data so placed goes to the
appropriate device..
Pin Configuration of Intel 8085A

RD & WR Control signals at pin no 32 and at pin no 31:
 Similarly to tell the external world the microprocessor is in input mode for READ
operation, it issues a control signal RD which is normally HIGH and active LOW.
 RD signal goes LOW during T2 state and goes HIGH again during T3 state similar to WR
signal.
 A LOW level an RD indicates the selected memory or I/O device is to be read and the data
bus is available for the data transfer.
 It is for the user to keep the appropriate 8-bit data either from the memory or I/O device
during this period.
Pin Configuration of Intel 8085A

 IO/M at pin no 34:

 IO/M is an output tri-state control signal.
 It is active both ways (HIGH as well as LOW).
 Whenever the address issued by the 𝑝on the address lines refers to the memory then the 𝑝
makes IO/M LOW throughout T1,T2,T3,T4,T5 & T6 states of the machine cycle to
indicate the external world that the address so sent belongs to the memory and data on the
BDB refers to the memory.
Pin Configuration of Intel 8085A

 IO/M at pin no 34:

 Whenever the address on the address lines refers to an I/O device the 𝜇𝑝 makes
IO/M control signal output HIGH to tell the external world that the address on the
address bus refers to I/O device and the data on the BDB refers to an I/O device.
Pin Configuration of Intel 8085A
 IO/M at pin no 34:
 Note that IO/M signal is LOW or HIGH as the case may be throughout six timing
slots T1,T2,T3,T4,T5 & T6 states.
 It is for the user to make use of this feature to develop proper interfacing circuitry
i.e., to generate the chip selected signals.
 In other words, a LOW IO/M signal enables the memory chips and a HIGH IO/M
signal enables the I/O device.
Pin Configuration of Intel 8085A

 Summary
 A15 – A8
 AD7–AD0


States for the Processor: RESET, WAIT, HOLD, HALT, T1, T2, T3, T4, T5 & T6
 ALE
 RD & WR
 IO/M
Pin Configuration of Intel 8085A Microprocessor

https://www.youtube.com/watch?v=I78iyzXQrP4
Pin Configuration of Intel 8085A

 READY at PIN NO 35:

 This is a control signal input.
 There are many peripheral devices which are slow in operation compared to the
microprocessor speed.
 Thus, there is a need for telling the 𝑝that the device so addressed by the 𝑝is not
ready for data transfer operation.
 The device, selected should have the ability to generate a control signal output
READY which shall be LOW if the device is not ready for data transfer operation and
goes HIGH when the device is READY for data transfer operation.
Pin Configuration of Intel 8085A

 READY at PIN NO 35:

Pin Configuration of Intel 8085A
 RESETIN at pin no.36 :
 It is an input control signal normally HIGH and active LOW. It is used to RESET the microprocessor to its
initial state.
 If RESET signal is held low for 600nsec (3 clock periods), this input forces the processor to do the following:
 (a) Program Counter (PC) is reset to (0000)H.
 (b) Instruction register (IR) is cleared i.e, ongoing instruction execution is discontinued.
 (c) All interrupts except TRAP are disabled with RST7.5, RST6.5 and RST5.5 also masked.
 (d) Serial Output Data line (SOD) is forced to 0.
 (e) During RESET IN LOW data, address and control bus are floated i.e., these buses are tri-stated
 (f) Because of the asynchronous nature of the RESET, the internal registers of the microprocessor and flags are
altered with unpredictable results.
 (g) The CPU remains in RESET state until the RESETIN goes high.
Pin Configuration of Intel 8085A
 RESETIN at pin no.36 :
 During power-on the microprocessor must be RESET. The necessary circuitry for resetting the 𝜇𝑝 is
shown in figure.
Pin Configuration of Intel 8085A
 X1, X2 terminal at pin nos.1 & 2 and CLK(OUT) at pin no.37 :
 The 8085A μ𝑝 has an on-chip oscillator with all the required circuitry except for the crystal, LC or RC
network that controls the operating frequency.
Pin Configuration of Intel 8085A
 X1, X2 terminal at pin nos.1 & 2 and CLK(OUT) at pin no.37 :

 A crystal is connected across X1 and X2 to provide a crystal frequency of fcrystal MHz.

 Because of the internal T – F/F the operating frequency of ∅1 clock is fcrystal/2 (half of crystal
frequency).
 The ∅1 clock is also buffered and sent out through pin no. 37 to tell the outside world as
CLK(OUT) signal.
 CLK(OUT) signal is used for synchronizing the peripheral devices with the μ 𝑝 operation.
Pin Configuration of Intel 8085A

 SID & SOD at PIN NO 5 & 4 :

 SID stands for SERIAL INPUT DATA and SOD stands for SERIAL OUTPUT DATA.
 These two pins are specially provided in 8085 𝑝for communicating with serial devices, like CRT,
TTY, and Printers etc.
 Microprocessor as and when needed uses SID and SOD lines for transfer of data bit by bit along the
same lines.
 The data on SID line is loaded into accumulator bit 7 whenever RIM instruction is executed.
 The output serial line SOD is set or reset as specified by the SIM instruction.
Pin Configuration of Intel 8085A
 INTERRUPT CONTROL SIGNALS:
 TRAP at pin no. 6, RST7.5 at pin no. 7, RST6.5 at pin no. 8, RST 5.5 at pin no. 9, and INTR at pin
no. 10 are interrupt control signals input provided for interrupting the 𝑝while it is executing the
programme.
 RST stands for RESTART. These interrupt control signal input can be broadly divided in to two
categories:
 (a) Non – maskable interrupts
 Non–maskable control signal inputs are those control signal inputs which can interrupt the 𝜇𝑝
programming execution once the power is ON.
 (b) Maskable interrupts
 The maskable interrupts are those control signal inputs which can be individually disabled or enabled as
and when necessary.
Pin Configuration of Intel 8085A
 INTERRUPT CONTROL SIGNALS:
 TRAP at pin no. 6, RST7.5 at pin no. 7, RST6.5 at pin no. 8, RST 5.5 at pin no. 9, and INTR at pin
no. 10 are interrupt control signals input provided for interrupting the 𝑝while it is executing the
programme.
 RST stands for RESTART. These interrupt control signal input can be broadly divided in to two
categories:
 (a) Non – maskable interrupts
 Non–maskable control signal inputs are those control signal inputs which can interrupt the 𝜇𝑝
programming execution once the power is ON.
 (b) Maskable interrupts
 The maskable interrupts are those control signal inputs which can be individually disabled or enabled as
and when necessary.
Pin Configuration of Intel 8085A
 INTERRUPT CONTROL SIGNALS:
Pin Configuration of Intel 8085A
 TRAP at pin no.6:
 TRAP control signal input of Intel 8085A processors is a non-maskable (NMI) RESTART vectored
interrupt.
 When the power is ON, it is enabled and no enable interrupt command is required.
 TRAP has the highest priority of any interrupt.
 It is both rising edge and level sensitive interrupt i.e. it becomes active at the Lo-Hi edge but must
stay high until it is sampled and recognized.
 Whenever this interrupt is recognized, it forces the 8085A to perform a CALL 0024H instruction,
means when the current instruction execution is over, the program counter (PC) is loaded with
0024H so that the CPU starts executing the program from 0024H.
Pin Configuration of Intel 8085A
 INTR at pin no.10:
 This is the lowest priority interrupt request in the 8085A processor and is used as a general purpose interrupt.
 An input of INTR=1 implies some external device has put up an interrupt and wants the CPU to execute an
appropriate service routine.
 The 8085A monitors the status of the INTR line by sampling it in the last but one clock cycle of each
instruction and during HOLD & HALT states.
 If the interrupt structure of the 8085A is enabled when INTR is sampled high, the PC will not be
incremented and an interrupt acknowledge signal (I N T A = 0) will be issued by the μ 𝑝 in response to INTR.
 It is now the responsibility of the interrupting device to issue a RESTART or CALL instruction so that the
8085A can jump to the proper interrupt service subroutine.
 The INTR is enabled by executing an EI instruction and is disabled by executing a DI instruction.
 Disabled means INTR will not be acknowledged.
 It is also disabled by RESET and immediately after an interrupt is acknowledged.
Pin Configuration of Intel 8085A
 RST5.5, RST6.5 & RST7.5:
 These are 8085A’s maskable vectored interrupt inputs.
 They operate exactly like INTR except for the following:
 1. The RESTART instruction is automatically inserted by internal logic. It does not have to be provided
from outside.
 These instructions are:
 RST 5.5 identical to CALL 002C H.
 RST 6.5 identical to CALL 0034 H
 RST 7.5 identical to CALL 003C H
 Restart instructions are special 1-byte unconditional CALL instructions. The address for any RST can be
calculated multiplying the RST number with 8 and converting it into hexa.
 E.g. for RST5.5 the address is 5.5x8 = 44D = 002C H
Pin Configuration of Intel 8085A
 RST5.5, RST6.5 & RST7.5:
 These are 8085A’s maskable vectored interrupt inputs.
 They operate exactly like INTR except for the following:
 1. The RESTART instruction is automatically inserted by internal logic. It does not have to be provided
from outside.
 These instructions are:

 RST 5.5 identical to CALL 002C H.

 RST 6.5 identical to CALL 0034 H
 RST 7.5 identical to CALL 003C H
 Restart instructions are special 1-byte unconditional CALL instructions. The address for any RST can be calculated
multiplying the RST number with 8 and converting it into hexa.
 E.g. for RST5.5 the address is 5.5x8 = 44D = 002C H
Pin Configuration of Intel 8085A

 RST5.5, RST6.5 & RST7.5:

 2. RST7.5 is an edge (Low to High) sensitive interrupt unlike RST6.5, RST5.5 and INTR which are level
(High) triggered.
 3. These three interrupts can be individually masked or unmasked using SIM instructions.
 4. They have higher priority than INTR. Among them RST7.5 has the highest priority and RST5.5 has the
lowest priority.
 Like the INTR, whenever any of these interrupts is recognized it disables all the interrupts. These interrupts
can be enabled/disabled using EI/DI instruction.
Pin Configuration of Intel 8085A
 Status Signals S1 (33) and S0 (29):
 These two status signals along with IO/M signal output identify the type of the machine cycle being executed
by the 8085A.
 These signals are issued (or become valid) at the beginning of the machine cycle and remain stable throughout
the machine cycle.
 The seven types of machine cycles are:
 1. Opcode Fetch Machine Cycle (OFMC)
 2. Memory Read Machine Cycle (MRMC)
 3. Memory Write Machine Cycle (MWRMC)
 4. I/O Read Machine Cycle (IORMC)
 5. I/O Write Machine Cycle (IOWRMC)
 6. Interrupt Acknowledge Machine Cycle (INTAMC)
 7. Bus Idle Machine Cycle. (BIMC)
Pin Configuration of Intel 8085A
 Status Signals S1 (33) and S0 (29):
Pin Configuration of Intel 8085A

 HOLD at pin no 39 and HLDA at pin no 38:

 HOLD (Hold) is a control signal input and HLDA (Hold acknowledge) is a control signal output.
 These two signals are used for hand shaked control during DMA operation (Direct Memory Access).
 These two signals are used where there is more than one CPU like devices sharing the same system bus.
 The device asking for DMA makes the HOLD signal input HIGH.
 The processor which continuously monitors the HOLD signal input during each machine cycle recognizes that
an external device is requesting for a DMA (i.e., the control of address bus, data bus, RD , WR and IO/M )
completes its current machine cycle in, thereafter, tri states the address bus, data bus and RD , WR and IO/M
control signals and then enters into a HOLD state THOLD.
Pin Configuration of Intel 8085A

 HOLD at pin no 39 and HLDA at pin no 38:

 Also, while entering the HOLD state the μ𝑝 issues the HOLD acknowledge signal HLDA high at pin no. 38.
 The external device asking for DMA monitors the HLDA control signal continuously and knows that the μ 𝑝
has gone into HOLD state when HLDA is found HIGH.
 Therefore, data bus, address bus, RD , WR and IO/M control signals which are tri-stated with respect to the μ 𝑝
are in the exclusive control of the external device asked for DMA.
Pin Configuration of Intel 8085A
 HOLD at pin no 39 and HLDA at pin no 38:
Pin Configuration of Intel 8085A
 Summary
 READY
 RESETIN
 X1, X2 and CLK(OUT)
 SID & SOD
 INTERRUPT CONTROL SIGNALS
 TRAP
 RST7.5
 RST6.5
 RST 5.5
 INTR
 Status Signals S1 and S0
 HOLD and HLDA
Pin Configuration of Intel 8085A
 Assignment
1. With the help of diagram show how de-multiplexing of address/data lines AD0- AD7 can be
achieved?
2. Explain functions of following pins of 8085:
IO/M, RD, WR

3. Explain the function of following pins in 8085.

SOD, HLDA, READY & TRAP.

4. What is interrupt? What are the interrupts available in 8085 microprocessor? Write interrupt vector
table for vectored interrupts. Explain SIM and RIM instructions.
Internal Architecture of Intel 8085A
 The functional block diagram of 8085A
 It consists of five essential blocks.
 (1) Arithmetic Logic Section
 (2) Register Section
 (3) The Interrupt Control Section
 (4) Serial I/O Section
 (5) The Timing And Control Unit
Internal Architecture of Intel 8085A

 There is an internal bi-directional data bus of 8-bit wide.

 This bus is used to transfer data and instructions among various internal registers.
 Higher order address bus (A15-A8) and time-multiplexed lower order address data
bus (AD7-AD0) are the external buses and used to interface peripherals and memory
chips to CPU.
Internal Architecture of Intel 8085A

 Address buffer and address/data buffers isolate the internal data bus from the external
address bus and address/data bus and drive the external address bus and address/data
bus.
 The CPU can send the address of desired memory locations and I/O chip through
these buffers.
Internal Architecture of Intel 8085A

1. Arithmetic & Logic Section:

 This section consists of:
 (a) Accumulator (A)
 (b) Temporary Register (TR)
 (c) Flag Register (FR)
 (d) Arithmetic Logic Unit (ALU)
Internal Architecture of Intel 8085A

1. Arithmetic & Logic Section:

 This section consists of:
 (a) Accumulator (A)
 (b) Temporary Register (TR)
 (c) Flag Register (FR)
 (d) Arithmetic Logic Unit (ALU)
Internal Architecture of Intel 8085A

a. Accumulator (A)
 Arithmetic and/or logic operations on one or two operations are the basic data
transformations implemented in a μρ, one of these two operands is always in the
accumulator.
 Accumulator is an 8-bit register accessible to the user is connected to the 8-bit
internal data bus.
 The content of the accumulator is always available at this two state output as one
of the operands for the ALU.
Internal Architecture of Intel 8085A

a. Accumulator (A)
 The contents of the accumulator can be manipulated through instructions.
 Its content can be incremented and decremented.
 The content of the memory location can be transferred to the accumulator and
vice-versa.
 The result of arithmetic/ logical operations carried out by ALU is also stored back
in the accumulator.
 In other words, it accumulates the result of the operation, hence, the name
accumulator.
Internal Architecture of Intel 8085A

b. Temporary registrar (TR):

 This is an 8-bit register not accessible to the user.
 It is used by the processor for internal operations.
 The second operand as and when necessary is loaded in to this register by the
microprocessor before the desisted operation takes placed in the ALU.
 The temporary register has 8-bits two state output. The second operand is always
available at this output.
Internal Architecture of Intel 8085A
c. Arithmetic Logical Unit (ALU):
 ALU is a combination logic block which performs the desired operation on the two
operands.
 The contents of the accumulator and the temporary register are the inputs to the ALU.
 This is governed by the control signals generated by the timing and control unit.
 The various arithmetic and logical operations that can be performed by ALU are:
 Binary addition, subtraction, increment and decrement,
 Logical AND, OR and EX-OR,
 Complement,
 Rotate left of right.
Internal Architecture of Intel 8085A
d. Flags register:
 The ALU influences a number of flip flops called flags which store information
related to the results of arithmetic and logical operations.
 Taken together this flags constitute a flag register.
 Flag register is an 8-bit register accessible to the user through instruction.
 Each bit in the flag register has a specific function. Only 5 bits out of 8 bits are
used as shown below:
Internal Architecture of Intel 8085A

d. Flags register:
 The three crossed bit are redundant bits and not used.
 They can be either ‘0’ or ‘1’ but normally they are forced to be zero.
 The other five bits are affected as a result of execution of an instruction.
 All instructions do not affect these flags e.g. data transfer operation do not affect
these flags.
Internal Architecture of Intel 8085A

CY (Carry) Flag bit :

 This particular bit is SET (=1) if there is a carry from the MSB position during an
addition operation or if there is a borrow during the subtraction operation
otherwise the flag is reset (=0).
 The processor, by design, does the subtraction operation also by taking 2’s
complement of one operand and adding it to another operand.
Internal Architecture of Intel 8085A

P (Parity) Flag bit :

 The parity flag test for the number of ‘1’s in the accumulator.
 If the accumulator holds on an even number of 1’s, it is said that even parity
exists and the parity flag is set to ‘1’.
 However, if the accumulator holds an odd number of ‘1’ it is called odd parity
and the parity flag is reset to ‘0’.
Internal Architecture of Intel 8085A

AC (Auxiliary Carry) Flag bit :

 This bit is set if there is a carry from b3 bit to b4 bit of accumulator during
addition operation otherwise it is reset.
 The AC flag is useful for BCD arithmetic and is used in a particular instruction
known as DAA (Decimal Adjust Accumulator).
Internal Architecture of Intel 8085A

Z (Zero) Flag bit:

 Zero flag bit is SET if the result of an operation is zero, otherwise it is RESET.
Sign Flag bit:
 The sign flag is set to the condition of the most significant bit of the accumulator
following the execution of arithmetic or logical operation.
 These instructions use the MSB of the data (result) to represent the sign of the
number contained in the accumulator.
 A set sign flag represents a negative number, where as a reset flag means a
positive number.
Internal Architecture of Intel 8085A

Assignment:
What are the flags after these operations:
 9B h + A5 h.
 9B h - A5 h
Internal Architecture of Intel 8085A
2. Register Section:
Internal Architecture of Intel 8085A
2. Register Section:
Internal Architecture of Intel 8085A

2. Register Section:
 General Purpose Registers
 There are six 8-bit general purpose registers designated as B, C, D, E, H and L.
 All these registers are accessible to the user. It means their contents can be read without destroying it
or some new data can be written into it through instructions.
 These registers constitute a register array like a small on-chip RAM with addressable memory
location.
Internal Architecture of Intel 8085A

2. Register Section:
 Program Counter:
 This is a 16-bit register accessible to the user.
 It is a special purpose register and it always contains the address of the next instruction to be fetched
from the program memory and executed by the CPU in a program sequence.
 Thus the program counter keeps the track of the program execution in which instructions are to be
executed next.
 When the microprocessor is RESET, the CPU initializes the PC to 0000 H. Therefore, the first
instruction of the program should be at 0000 H in the memory address space of the CPU.
Internal Architecture of Intel 8085A
2. Register Section:
 Stack Pointer Register:
 The stack is a storage area of the processor.
 It consists of number of sequential and RWM locations in which microprocessor saves the internal
register contents during subroutine calls and interrupts so that they will not be changed or destroyed
by a subroutine.
 8085A μ𝑝 can address directly 64K memory locations. This is known as directly addressable memory
space starting from the address 0000H to FFFFH.
 This entire memory area is usually divided by the user into program area, data area and stack area.
 It is for the user to see that program area and data area do not overlap with that of stack memory area.
 The size of the stack memory area depends upon the application.
Internal Architecture of Intel 8085A
2. Register Section:
 Stack Pointer Register:
Internal Architecture of Intel 8085A

2. Register Section:
 Stack Pointer Register:
 Since the stack pointer always holds the address of the last byte of data pushed onto the stack,
therefore, when PUSH B instruction is executed, the stack pointer is decremented by 1 and the
contents of the (B) register are copied onto the stack at that address.
 The stack pointer is decremented again, and the contents of the (C) register are copied to that address.
Just after the execution of the PUSH B instruction, the situation is shown in fig.
Internal Architecture of Intel 8085A
2. Register Section:
 Stack Pointer Register:
Internal Architecture of Intel 8085A

2. Register Section:
 Stack Pointer Register:
 Similarly, to store the contents of (D,E) register pair PUSH D instruction is used.
 The meaning of this instruction is push the contents of the (D,E) pair onto the stack to save them
there as shown in figure just after the execution.
Internal Architecture of Intel 8085A
2. Register Section:
 Stack Pointer Register:
Internal Architecture of Intel 8085A

2. Register Section:
 Stack Pointer Register:
 Since the contents of (B,C) & (D,E) register pairs are stored at the top of the stack, these registers are
now available for further computation in the subroutine.
 At a later stage of execution of the program after utilizing B, C, D, E registers, there may be a need to
restore the original contents to the respective registers. E.g. at the end of the subroutine, the data is
restored to the proper register.
Internal Architecture of Intel 8085A

2. Register Section:
 Stack Pointer Register:
 The restoration of the contents is a READ operation from the stack and is known as POP operation. A
POP register instruction copies the stored data from the stack back into the indicated register pair.
 Just before the execution of POP instruction, let us say the situation is as shown below:
Internal Architecture of Intel 8085A
2. Register Section:
 Stack Pointer Register:
Internal Architecture of Intel 8085A
2. Register Section:
 Stack Pointer Register:
 Note that registers (B), (C), (D) and (E) have some different contents because these registers are used
in the subroutine.
 To restore the contents of (B,C) register pair, POP B instruction is used. Whenever this instruction is
executed, the contents from the top of the stack are read and written into the (B,C) register pair.
 To restore the contents (D,E) register pair POP D instruction is used. The question is in which
sequence these instructions are to be executed so that the contents are restored properly.
 The obvious sequence in POP D first & then POP B i.e., the data must be poppedoff in the reverse
order from which it was pushed.
 This type of stack is called Last-in-First-out (LIFO) memory.
Internal Architecture of Intel 8085A
2. Register Section:
 Stack Pointer Register:
 Just after the execution of POP D & POP B instructions,
the situation is as shown in figure:
Internal Architecture of Intel 8085A
2. Register Section:
 Stack Pointer Register:
 From the above discussion, following points emerge:
1. The stack pointer always points to the top of the stack up to which it is full with relevant data.
2. Storing or saving the data from the registers on stack is known as PUSH operation.
3. The restoring or reading data from the stack onto certain internal registers is known as POP
operation.
4. The stack operates on Last-in-first-out (LIFO) basis.
5. The stack pointer can be initialized to the bottom of the stack but bottom of the stack cannot be
utilized to store any useful data.
6. It is for the user to see that the program area does not overlap with stack area.
Internal Architecture of Intel 8085A

2. Register Section:
 W-Z:
 (W) and (Z) are two 8-bit temporary registers not accessible to the user.
 They are exclusively used for the internal operation by the microprocessor.
 These registers are used either to store 8-bit of information in each (W) and (Z) registers or a 16-bit
data in (W,Z) register pair with lower order 8-bits in (Z) and higher-order 8-bits in (W) register.
Internal Architecture of Intel 8085A

2. Register Section:
 W-Z:
 When a 3-byte instruction containing 2-byte address is to be executed by the μ 𝑝, the first byte is the
(op-code byte) which is fetched and then decoded by the decoder.
 Then two memories read machine cycles are executed one by one to read the two-byte address, one
in each machine cycle and placed in (W,Z) register pair.
 During instruction execution, in next machine cycle, the address in (W,Z) register pair is transferred
to the address latch to address memory or I/O for data transfer.
Internal Architecture of Intel 8085A
2. Register Section:
 Increment-Decrement Address Latch:
 It is another 16-bit internal register latch available in the register section for internal operations and is
not accessible to the user.
 The address latch serves two functions.
 First, it selects an address to be sent out from the program counter, from the stack pointer, or from
one of the 16-bit register pairs.
 Second, it latches this address onto the address lines for the required time.
 The 16-bit addresses from 8085A allow the microprocessor up to 216 memory locations through
A15-A8 and AD7-AD0 lines.
 An increment/decrement register allows the contents of any of the 16-bit registers to be incremented
or decremented.
Internal Architecture of Intel 8085A
2. Register Section:
 Instruction Register & Instruction Decoder:
 The first word of an instruction is the operation code, i.e., binary code for that instruction. Therefore, in the first
machine cycle of any instruction μ𝑝 fetches the instruction from the memory .
 The op-code representing the instruction to be executed is fetched from the (program) memory location pointed to by
(PC) and loaded into the instruction register (IR).
 The IR passes this op-code to the instruction decoder which interprets this op-code appropriately in order to decide
what operation needs to be done for executing this instruction.
 The instruction decoder tells the control unit the type of instruction to be executed; the number of machine cycles
necessary to execute the instruction etc.
 In response, the control unit generates all the necessary control signals which go into the different internal block of the
microprocessor.
 These different control signals are generated by what is known as Micro-programming technique. Micro-
programming means the microprocessor instruction decoding operated like a small version of a μ 𝑝 itself.
 As the μ𝑝 goes through the fetch and execute cycles, the microprogramming logic goes through a series of fetch and
executes cycles.
Internal Architecture of Intel 8085A
2. Register Section:
 Instruction Register & Instruction Decoder:
 E.g. if the instruction is ADI 04H, then the first binary code read by the μ𝑝 is C6H into the
(IR).
 After decoding this, the decoder will recognize that another memory read cycle is required to
read 04H to be added to the number in the accumulator.
 The decoder will direct the control circuit to send out another memory read pulse and
transfers the data coming on the data bus into the temporary register (Temp), so that it can be
added to the accumulator.
 When the addition is completed the control circuit directs the result back to the accumulator.
 The program counter is then incremented to point the next memory address and send out
another memory read pulse to read the μ 𝑝 code of next instruction from memory.
Internal Architecture of Intel 8085A

3. Interrupt Control Section :

 Sometimes it is necessary to interrupt the execution of the main program to answer a
request from an I/O device.
 For instance, an I/O device may send an interrupt signal to interrupt control unit to
indicate that data is ready for input.
 The μ𝑝 temporarily stops what it is doing, inputs the data and then returns to what it
was doing.
 To enable the processor to service the device requesting service through interrupt,
processor accepts and issues control signals through interrupt control section.
Internal Architecture of Intel 8085A
4. Serial I/O Control:
 Sometimes, I/O devices work with serial data rather than parallel.
 In this case, the serial data stream from an input device must be converted to 8-
bit parallel data before the computer can use it.
 Likewise the 8-bit data out of a processor must be converted to serial form
before a serial output device can use it.
 The SID (Serial Input Data) input is where serial data enters the 8085A.
 The SOD (Serial Output Data) output is where the serial data leaves the 8085A.
 Two instructions known as SIM & RIM allow the user to perform the serial
parallel conversion needed for serial I/O device.
Internal Architecture of Intel 8085A
5. Timing and Control section:
 The timing and control section supervise the complete operation of the 𝜇𝑝.
 The on-chip clock oscillator which produces the internal clock is a part of this section.
 The timing and control section also has a state generator circuit to generate 10
different states namely T1, T2, T3, T4, T5, T6, TRESET, THALT, TWAIT and
THOLD.
 State generator is a multi-mode counter. The next state of the state generator from the
present state is decided by many of the control signals input like READY, HOLD,
Interrupt control signals - TRAP, RST7.5, RST6.5, RST5.5 and INTR.
 In each state this section generates many control signals for executing the instruction
fetched.
Internal Architecture of Intel 8085A
5. Timing and Control section:
 The operation of the 𝜇𝑝 is cyclic in natural.
 During the normal operation from the word GO, 𝑝sequentially fetches and
executes one instruction after another until a HALT instruction is executed.
 The fetching and execution of a single instruction constitutes an instruction cycle.
 The instruction cycle consists of one or more read or write operation to memory
or an I/O device.
 Each memory and I/O reference requires a mechanic cycle.
 In other words every time a byte of data is move from CPU to I/O or memory or
from memory or I/O to CPU, a machine cycle is required.
Internal Architecture of Intel 8085A
 Machine Cycles:
 There are seven different kinds of machine cycles in the 8085 A:
1. Opcode Fetch Machine Cycle (OFMC)
2. Memory Read Machine Cycle (MRMC)
3. Memory Write Machine Cycle (MWRMC)
4. I/O Read Machine Cycle (IORDMC)
5. I/O Write Machine Cycle (IOWRMC)
6. Interrupt Acknowledge Machine Cycle (INTAMC)
7. Bus Idle Machine Cycle (BIMC)
Instruction and assembly language Program
 Instruction Set:
 The 74 instructions available in the 8085A can be divided into five groups
depending on their function::
1. Data Transfer group
2. Arithmetic group
3. Logic group
4. Branch group
5. Stack Machine Control group
Instruction and assembly language Program
 Data Transfer Group:
 It consists of 15 basic instructions and 86 variations.
 The basic operation involved is DATA transfer between two register of a
microprocessor system.
 One of the register is always located in the 𝑝itself; the other may be located in one
of the following
1) An I/o device
2) Memory
3) The microprocessor
Instruction and assembly language Program
 Data Transfer Group:
1. MOV r1, r2:
 This is an ALP statement. MOV is the mnemonic for move operation. r2 is the
source register and r1 is the destination register in the operand fields.
 The meaning of the instruction is “Move the contents of the register r2 into r1”. The
content of register r2 is not destroyed. Content of r1 is destroyed and new value
form r2 takes it place.

r1 r2
Instruction and assembly language Program

 Data Transfer Group:

2. MOV r, M:
 The meaning of this instruction is “Move the content of the memory location whose
address is available into (H,L) pair into the internal general purpose register r”.

r M(H,L)
Instruction and assembly language Program

 Data Transfer Group:

3. MOV M, r:
 The meaning of this instruction is “Move the content of the memory location whose
address is available into (H,L) pair into the internal general purpose register r”.

M(H,L) r
Instruction and assembly language Program
 Data Transfer Group:
4. MVI r, DATA:
 DATA is the symbolic name given to 8-bit data which is immediately available as
second byte of the instruction. Therefore, the source of data is the 2nd byte of the
instruction itself.
 The meaning of the instruction is “Move 8-bit data immediately available as a 2nd
byte of the instruction itself into the destination register r”.

r
DATA
Instruction and assembly language Program

 Data Transfer Group:

5. MVI M, DATA:
 The meaning of the instruction is “Move 8-bit data available immediately as a 2nd
byte of the instruction to the memory location whose address is available in memory
pointed by (H, L) register pair”.

M(H,L)
DATA
Instruction and assembly language Program
 Data Transfer Group:
6. LXI rp, DDATA:
 DDATA stands for double-data, a symbolic name given to 16-bit data available
immediately as the 2nd & 3rd bytes of the instruction.
 ”rp”stands for register pair.
 The meaning of the instruction is “Load the 16 bit data immediate available as the
2nd & 3rd bytes of the instruction into register pair rp”.

rpl
DATA1
rph
Instruction and assembly language Program
 Data Transfer Group:
7. LDA ADDR:
 ADDR is the symbolic name given to the 16 bit address directly available in the
instruction.
 LDA is the mnemonic for LOAD ACCUMULATOR DIRECT.
 The meaning of the instruction is “Load the content of the memory location whose
address is directly available in the instruction as 2 nd and 3rd bytes into the
accumulator”.
A (ADDR)
Instruction and assembly language Program

 Data Transfer Group:

8. STA ADDR:
 STA is the mnemonic for the STORE ACCUMULATOR DIRECT.
 The meaning of the instruction is “Store the content of the accumulator into the
memory location whose address is directly available in the instruction itself as a 2nd
& 3rd byte of instruction”.

(ADDR) A
Instruction and assembly language Program
 Data Transfer Group:
9. LHLD ADDR:
 LHLD is the mnemonic for LOAD (H,L) REGISTER PAIR DIRECT.
 The meaning of the instruction is “Load the content of the memory location whose
address is directly available as 2nd & 3rd byte of the instruction to register L and the
content of the memory location at next higher address to the register H”.
 This is a 3-byte instruction.

L (ADDR)
H
Instruction and assembly language Program
 Data Transfer Group:
10. SHLD ADDR:
 SHLD is the mnemonic for STORE (H, L) REGISTER PAIR DIRECT.
 The meaning of the instruction is the “Store the content of (L) register into the
memory location whose address is available as 2nd & 3rd byte of the instruction
itself and store the content of (H) register into the memory location whose address is
next higher address”.
 This is a 3-byte instruction.
(ADDR)
L
(ADDR+1)
Instruction and assembly language Program
 Data Transfer Group:
11. LDAX rp:
 LDAX is the mnemonic for LOAD ACCUMULATOR INDIRECTLY.
 The meaning of the instruction is “Load the accumulator from the memory location
whose address is available in a register pair specified in the instruction”.

A (H, L)
A (B, C)
A (D, E)
Instruction and assembly language Program
 Data Transfer Group:
12. STAX rp:
 STAX is the mnemonic for store accumulator indirectly using register indirect
addressing mode.
 The meaning of the instruction is “Store the content of accumulator in the memory
location whose address is available in register pair specified in the instruction”.

(H, L) A
(B, C) A
(D, E) A
Instruction and assembly language Program
 Data Transfer Group:
13. IN PORT:
 PORT is the symbolic name given to 8-bit address of the input device available as a
2nd byte of the instruction.
 IN is the mnemonic for INPUT.
 The meaning of the instruction is “Input an 8-bit data from the input device whose
address is available as a 2nd byte of the instruction and load it into accumulator”.

A I/O
(ADDR)
Instruction and assembly language Program
 Data Transfer Group:
14. OUT PORT:
 PORT is the symbolic name given to the 8-bit address of the output device available
as the 2nd byte of instruction.
 OUT is the mnemonic for OUTPUT.
 The meaning of the instruction is “Output the content of accumulator to an output
device whose address is available in the instruction As the 2nd byte of the
instruction”.

I/O (ADDR)
Instruction and assembly language Program

 Data Transfer Group:

15. XCHG:
 The meaning of the instruction is “Exchanged the contents of (H, L) register pair
with the contents of (D,E) pair”.

(D, E) (H,
L)
Instruction and assembly language Program
 ARITHMETIC GROUP:
 The instructions of this group perform the arithmetic operations on the operands.
 Normally two operands are necessary for any arithmetic operation.
 One of the operand is always assumed to be available in accumulator. The other
operand can be made available in one of the three locations:
a. In an internal general purpose register (r).
b. In a memory location pointed by M-pointer i.e., (H, L) pair.
c. Immediately in the instruction itself as a 2nd byte.
 All the flags of Flag register are affected as per standard rule.
 There are 20 basic instructions in this group.
Instruction and assembly language Program
 ARITHMETIC GROUP:
1. ADD r:
 This is a single byte instruction.
 The meaning of the instruction is “Add the content of register (r) to the content of
accumulator and store the result back into the accumulator”.

A A+r
Instruction and assembly language Program
 ARITHMETIC GROUP:
2. ADD M:
 This is a single byte instruction.
 The meaning of the instruction is “Add the content of memory location whose
address is in (H,L) pair to the content of accumulator and store the result back into
the accumulator”.

A A+
M(H, L)
Instruction and assembly language Program

 ARITHMETIC GROUP:
3. ADI DATA:
 It is a two byte instruction.
 The meaning of the instruction is “Add the content available as the second byte of
the instruction to the content of accumulation and store the result back into the
accumulator”.

A A+
DATA
Instruction and assembly language Program

 ARITHMETIC GROUP:
4. ADC r:
 It is a single byte instruction.
 The meaning of the instruction is “Add the content of register (r) to the content of
accumulator with carry and store the result back into accumulator”.

A A+r+
CY
Instruction and assembly language Program
 ARITHMETIC GROUP:
5. ADC M:
 It is a single byte instruction.
 The meaning of the instruction is “Add the contents of memory location whose
address is available in (H, L) pair to the contents of accumulator with carry and store
the result back into accumulator”.

A A + (H, L) +
CY
Instruction and assembly language Program

 ARITHMETIC GROUP:
6. ACI DATA:
 It is a two byte instruction.
 The meaning of the instruction is “Add the content available as the second byte of
instruction itself to the content to accumulator with carry and store the result back
into the accumulator”.

A A + DATA +
CY
Instruction and assembly language Program

 ARITHMETIC GROUP:
7. SUB r:
 This is a single byte instruction.
 The meaning of the instruction is “Subtract the content of register (r) from the
content of accumulator and store the result back into the accumulator”.

A A-r
Instruction and assembly language Program
 ARITHMETIC GROUP:
8. SUB M:
 This is a single byte instruction.
 The meaning of the instruction is “Subtract the content of memory location whose
address is in (H,L) pair from the content of accumulator and store the result back
into the accumulator”.

A A – M(H, L)
Instruction and assembly language Program

 ARITHMETIC GROUP:
9. SUI DATA:
 It is a two byte instruction.
 The meaning of the instruction is “Subtract the content available as the second byte
of the instruction from the content of accumulation and store the result back into the
accumulator”.

A A – DATA
Instruction and assembly language Program

 ARITHMETIC GROUP:
10. SBB r:
 It is a single byte instruction.
 The meaning of the instruction is “Subtract the content of register (r) from the
content of accumulator with borrow and store the result back into accumulator”.

A A – r – CY
Instruction and assembly language Program

 ARITHMETIC GROUP:
11. SBB M:
 It is a single byte instruction.
 The meaning of the instruction is “Subtract the content of memory location whose
address is available in (H, L) pair from the content of accumulator with borrow and
store the result back into accumulator”.

A A – M(H, L)
– CY
Instruction and assembly language Program
 ARITHMETIC GROUP:
12. SBI DATA:
 It is a two byte instruction.
 The meaning of the instruction is “Subtract the content available as the second byte
of instruction itself from the content to accumulator with borrow and store the result
back into the accumulator”.

A A – DATA –
CY
Instruction and assembly language Program

 ARITHMETIC GROUP:
13. INR r:
 It is a single byte instruction.
 The meaning of the instruction is “Increment the content of register (r) by 1 and
store the result back to the register (r)”.

r r+1
Instruction and assembly language Program

 ARITHMETIC GROUP:
14. INR M:
 It is a single byte instruction.
 The meaning of the instruction is “Increment the content of memory location by 1
whose address is available in (H, L) pair and stores the result back in the same
location”.

M(H, L) M(H,
L) + 1
Instruction and assembly language Program

 ARITHMETIC GROUP:
15. DCR r:
 It is a single byte instruction.
 The meaning of the instruction is “Decrement the content of register (r) by 1 and
store the result back to the register (r)”.

r r-1
Instruction and assembly language Program
 ARITHMETIC GROUP:
16. DCR M:
 It is a single byte instruction.
 The meaning of the instruction is “Decrement the content of memory location by 1
whose address is available in (H, L) pair and stores the result back in the same
location”.

M(H, L) M(H,
L) – 1
Instruction and assembly language Program

 ARITHMETIC GROUP:
17. INX rp:
 It is a single byte instruction.
 The meaning of the instruction is “Increment the content of register pair (rp) by 1
and store it in same register pair”.

(H, L) (H, L) +
1
(B, C) (B, C) +
1
Instruction and assembly language Program
 ARITHMETIC GROUP:
18. DCX rp:
 It is a single byte instruction.
 The meaning of the instruction is “Decrement the content of register pair (rp) by 1
and store it in same register pair.

(H, L) (H, L) –
1
(B, C) (B, C) –
1
Instruction and assembly language Program
 ARITHMETIC GROUP:
19. DAD rp:
 It is a single byte instruction.
 The meaning of the instruction is double precision addition, i.e., “Add the contents
of (H,L) register pair with the contents of register pair (rp) and store the result back
into (H,L) register pair”.

(H, L) (H, L) +
rp
Instruction and assembly language Program
 ARITHMETIC GROUP:
20. DAA:
 It is a single byte instruction. The meaning of the instruction is decimal adjust
accumulator.
 It is specifically used for BCD addition operation. It adjusts the content of
accumulator to two digit BCD.
Instruction and assembly language Program
 ARITHMETIC GROUP:
20. DAA:
 This instruction is used just after the addition operation. Whenever DAA is executed
the following checks and corrections are made:
1. If the lower order 4-bits A3A2A1A0 is an illegal BCD code or if AC is SET then 06H is
added to accumulator.
2. Thereafter, if the higher order 4-bits A7A6A5A4 is an illegal BCD code or if CY is SET
then 60 H is added to accumulator else no action.
Instruction and assembly language Program
 LOGICAL GROUP:
 It consists of 19 basic instructions.
 There are three basic logic operation AND, OR & XOR.
 Logical operation takes place bit by bit.
 If two operands are involved in the instruction, the first operand is assumed to be in the
accumulator.
 The second 8-bit operand is available in:
a. the internal general purpose register
b. in the memory location pointed to by the M-pointer
c. the 2nd byte of the instruction itself.
 The result of the logical operation is stored back in the accumulator.
Instruction and assembly language Program
 LOGICAL GROUP:
1. ANA r:
 This is a single byte instruction.
 The meaning of the instruction is “AND bit by bit the content of register (r) to the
content of accumulator and store the result back in the accumulator”.

𝑨 𝑨∩𝒓
Instruction and assembly language Program
 LOGICAL GROUP:
2. ANA M:
 This is a single byte instruction.
 The meaning of the instruction is “AND bit by bit the content of memory location
pointed by (H, L) register pair to the content of accumulator and store the result back
in the accumulator”.

𝑨 𝑨 ∩ 𝑴 ( 𝑯 , 𝑳)
Instruction and assembly language Program

 LOGICAL GROUP:
3. ANI DATA:
 It is a two byte instruction.
 The meaning of the instruction is “AND bit by bit the content available as a second
byte of instruction to the content of the accumulator and store the result back in the
accumulator”.

𝑨 𝑨 ∩ 𝑫𝑨𝑻𝑨
Instruction and assembly language Program

 LOGICAL GROUP:
4. XRA r:
 It is a single byte instruction.
 The meaning of the instruction is “Exclusively ORed bit by bit the content of register
(r) with the content of accumulator and store the result back into accumulator”.

𝑨 𝑨 ⨁𝒓
Instruction and assembly language Program

 LOGICAL GROUP:
5. XRA M:
 This is a single byte instruction.
 The meaning of the instruction is “Exclusively ORed bit by bit the content of memory
location pointed by (H, L) register pair to the content of accumulator and store the
result back in the accumulator”.

𝑨 𝑨 ⨁ 𝑴 ( 𝑯 , 𝑳)
Instruction and assembly language Program

 LOGICAL GROUP:
6. XRI DATA:
 It is a two byte instruction.
 The meaning of the instruction is “Exclusively ORed bit by bit the content of second
byte of the instruction with the content of accumulator and store the result back into
accumulator”.

𝑨 𝑨 ⨁ 𝑫𝑨𝑻𝑨
Instruction and assembly language Program

 LOGICAL GROUP:
7. ORA r:
 It is a single byte instruction.
 The meaning of the instruction is “ORed bit by bit the content of register (r) with the
content of accumulator and store the result back into accumulator”.

𝑨 𝑨⋃ 𝒓
Instruction and assembly language Program

 LOGICAL GROUP:
8. ORA M:
 This is a single byte instruction.
 The meaning of the instruction is “ORed bit by bit the content of memory location
pointed by (H, L) register pair to the content of accumulator and store the result back
in the accumulator”.

𝑨 𝑨 ⋃ 𝑴 ( 𝑯 , 𝑳)
Instruction and assembly language Program

 LOGICAL GROUP:
9. ORI DATA:
 It is a two byte instruction.
 The meaning of the instruction is “ORed bit by bit the content of second byte of the
instruction with the content of accumulator and store the result back into accumulator”.

𝑨 𝑨 ⋃ 𝑫𝑨𝑻𝑨
Instruction and assembly language Program
 LOGICAL GROUP:
10. CMP r:
 It is a single byte instruction.
 The meaning of the instruction “Compare the content of accumulator with the content of
register (r)”.
 Thus the contents of Acc & register (r) are not destroyed but as result of this operation
the flags are affected as per standard rule as given below:
 If
 (A) > (r) CY = 0, Z = 0
 (A) = (r) CY = 0, Z = 1
 (A) < (r) CY = 1, Z = 0
Instruction and assembly language Program
 LOGICAL GROUP:
11. CMP M:
 It is a single byte instruction.
 The meaning of the instruction is “Compare the content of accumulator with the
content of memory location whose address is available in (H, L) register pair”.
 If
 (A) > M(H, L) CY = 0, Z = 0
 (A) = M(H, L) CY = 0, Z = 1
 (A) < M(H, L) CY = 1, Z = 0
Instruction and assembly language Program

 LOGICAL GROUP:
12. CPI data:
 The meaning of the instruction is “Compare the content of accumulator with the 8-bit
data available in the instruction as immediate data byte”.
 If
 (A) > DATA CY = 0, Z = 0
 (A) = DATA CY = 0, Z = 1
 (A) < DATA CY = 1, Z = 0
Instruction and assembly language Program
 LOGICAL GROUP:
13. RLC:
 The meaning of the instruction is “Rotate left the content of the accumulator by one bit
without carry flag. The lower order bit & the CY flag are both set to the value shifted
out the high order bit position”.
Instruction and assembly language Program

 LOGICAL GROUP:
14. RRC:
 The meaning of the instruction is “Rotate right the content of the accumulator by one
bit without carry flag. The higher order bit & the CY flag are both set to the value
shifted out the lower order bit position”.
Instruction and assembly language Program
 LOGICAL GROUP:
15. RAL:
 The meaning of the instruction is “Rotate left the content of the accumulator by one bit
through the carry flag. The lower order bit set equal to the CY flag and CY flag is set
to the value shifted out of the A7 bit”.
Instruction and assembly language Program
 LOGICAL GROUP:
16. RAR:
 The meaning of the instruction is “Rotate right the content of the accumulator by one
bit through carry flag. The higher order bit is set equal to the CY flag and the CY flag
is set to the value shifted out the lower order bit position”.
Instruction and assembly language Program

 LOGICAL GROUP:
17. CMA:
 The meaning of the instruction is “Complement the content of accumulator bit by bit
and store the result back into the accumulator”.
Instruction and assembly language Program

 LOGICAL GROUP:
18. CMC:
 The meaning of the instruction is “Complement CY flag and store it back into the same
CY flag position”.
Instruction and assembly language Program

 LOGICAL GROUP:
19. STC:
 The meaning of the instruction is “Set the CY flag to “1””.

1
Instruction and assembly language Program
 BRANCH GROUP:
 This group of instructions is used to alter the normal sequential program flow and force the
program to proceed from a different point.
 Condition flags are not affected by any instruction in this group only program counter (PC)
is affected; sometimes stack is also affected.
 Branch instructions can be of two types: conditional & unconditional.
 Unconditional branch instructions simply cause the program to branch to the indicated instruction
whenever these instructions are encountered, i.e., (PC) is loaded with a new address.
 Conditional branch instructions examine the status of one of the four processor flags (Z, CY, P, S)
to determine if the specified branch instruction is to be executed. If the condition tested is TRUE,
it causes a branching to occur otherwise not. AC is not used for specifying condition.
Instruction and assembly language Program
 BRANCH GROUP:
 The 8 conditions that are tested are given below:
Instruction and assembly language Program
 BRANCH GROUP:
1. JMP ADDR:
 ADDR is the symbolic name given to the 16- bit address data available as the 2nd and
3rd bytes of the instruction. JMP is the mnemonic for jump.
 The meaning of the instruction is “Load the PC with the 16- bit data available in the
instruction itself as the 2nd and 3rd bytes of instruction so that the next instruction is
fetched from this address in the succeeding instruction cycle”.

PCL ADDR(L)
PCH ADDR(H)
Instruction and assembly language Program
 BRANCH GROUP:
2. Jcond ADDR:
 This is a 3-byte conditional jump instruction.
 There are 8 conditions that can be checked. Accordingly, there are 8-variations for this
instruction depending upon the conditions to be tested. They are JNZ, JZ, JNC, JC,
JPO, JPE, JP, and JM.

If the condition is true

PCL ADDR(L)
PCH ADDR(H)
Instruction and assembly language Program

 BRANCH GROUP:
3. CALL ADDR:
 This instruction is used for unconditional subroutine CALL.
 The starting address of the subroutine is Y3Y2Y1Y0, available immediately in the
instruction itself as 2nd and 3rd bytes of the instruction.
 The stack is made use of to store the return address before jumping to the subroutine.
The meaning of the instruction is
 “Save the return address on the top of the stack and thereafter, load the (PC) with the
16-bit address immediately available in the instruction as 2nd and 3rd bytes”.
Instruction and assembly language Program

 BRANCH GROUP:
3. CALL ADDR:
 This instruction is used for unconditional subroutine CALL.
 The starting address of the subroutine is Y3Y2Y1Y0, available immediately in the
instruction itself as 2nd and 3rd bytes of the instruction.
 The stack is made use of to store the return address before jumping to the subroutine.
The meaning of the instruction is
 “Save the return address on the top of the stack and thereafter, load the (PC) with the
16-bit address immediately available in the instruction as 2nd and 3rd bytes”.
Instruction and assembly language Program

 BRANCH GROUP:
3. CALL ADDR:
M(SP – 1) PCH
M(SP – 2) PCL
SP SP – 2
PCL ADDR(L)
PCH ADDR(H)
Instruction and assembly language Program

 BRANCH GROUP:
4. Ccond ADDR:
 This is also 3-byte instruction.
 2nd and 3rd bytes give the address of the subroutine. When this instruction is executed,
the 𝑝jump to the subroutine if the condition tested is TRUE.
 If the condition is not TRUE then 𝑝goes to execute the next instruction.
 The corresponding instructions are CNZ, CZ, CNC, CC, CPO, CPE, CP and CM.
Instruction and assembly language Program

 BRANCH GROUP:
4. Ccond ADDR:

If condition is true
M(SP – 1) PCH
M(SP – 2) PCL
SP SP – 2
PCL ADDR(L)
PCH ADDR(H)
Instruction and assembly language Program
 BRANCH GROUP:
5. RET (Unconditional Return):
 The meaning of the instruction is “Return to the main program from the subroutine
unconditionally”.
 Obviously RET instruction should be a part of the subroutine program.

PCL M(SP)
PCH M(SP + 1)
SP SP + 2
Instruction and assembly language Program
 BRANCH GROUP:
6. Rcond:
 Whenever this instruction is executed, 𝑝checks the conditional flags.
 If the condition is found true then the 𝑝returns to the main program by loading the
(PC) with the return address stored at the top of the stack. If the condition is found not
true then the next instruction of the subroutine will be executed.
 There are 8 variations in this statement depending upon CCC. They are RNZ, RZ,
If the condition is true
RNC, RC, RPO, RPE, RP and RM.
PCL M(SP)
PCH M(SP + 1)
SP SP + 2
Instruction and assembly language Program
 BRANCH GROUP:
7. RST n:
 This is a single byte unconditional subroutine call instruction. The address of the
subroutine is fixed depending upon the decimal number “n” in the instruction.
 The decimal number “n” can change from 0 to 7.

M(SP – 1) PCH
M(SP – 2) PCL
SP SP – 2
PC 8xn
Instruction and assembly language Program

 BRANCH GROUP:
8. PCHL:
 The meaning of the instruction is “Move the content of register (H) to the higher byte
of program counter (PCH) and move the content of register (L) to lower byte of
program counter (PCL)”.
 In this way the control is transferred to the memory location whose address is available
in (H, L) register pair.
PCH H
PCL L
Instruction and assembly language Program

 STACK GROUP:
 This group of instructions manipulates the stack.
 Unless otherwise specified, condition flags are not affected by any instruction of this
group.
 It is the user responsibility to define stack area and to initialize the stack pointer (SP)
with the bottom address before these instructions are used.
Instruction and assembly language Program

 STACK GROUP :
1. PUSH rp :
 The meaning of the instruction is “Push or save the contents of register pair (rpH, rpL)
on top of the stack”.
M(SP – 1) rpH
M(SP – 2) rpL
SP SP – 2
Instruction and assembly language Program
 STACK GROUP :
2. PUSH PSW (Push Processor Status Word):
 The meaning of the instruction is “Save or push the processor status word, comprising
of (A) and (F) register, on the top of the stack”.
 The accumulator & flag register together form a 16- bit word known as the processor
status word (PSW), ACC occupies the higher order 8-bits and flag register occupies the
lower order 8-bits in PSW.
M(SP – 1) A
M(SP – 2) F
SP SP – 2
Instruction and assembly language Program

 STACK GROUP :
3. POP rp:
 The meaning of the instruction is “Pop or load the content form the top of the stack
into register pair (rp)”.
rpL M(SP)
rpH M(SP + 1)
SP SP + 2
Instruction and assembly language Program
 STACK GROUP :
4. POP PSW (Push Processor Status Word):
 The meaning of the instruction is “Save or push the processor status word, comprising
of (A) and (F) register, on the top of the stack”.
 The accumulator & flag register together form a 16- bit word known as the processor
status word (PSW), ACC occupies the higher order 8-bits and flag register occupies the
lower order 8-bits in PSW.
F M(SP)
A M(SP + 1)
SP SP + 2
Instruction and assembly language Program

 STACK GROUP :
5. XTHL:
 The meaning of the instruction is “Exchange the contents from the top of the stack
with the contents of (H, L) register pair”.

L M(SP)
H M(SP + 1)
Instruction and assembly language Program

 STACK GROUP :
6. SPHL:
 The meaning of the instruction is “Move the contents of register pair (H, L) to 16-bit
register stack pointer (SP)”.

SPH H
SPL L
Instruction and assembly language Program

 MACHINE CONTROL INSTRUCTIONS:

1. EI (Enable interrupts):
 The interrupt system is disabled just after RESET operation.
 The interrupt system is enabled using EI instruction.
 When this instruction is executed, then INTE F/F is set so that all the interrupts are
enabled and 8085 A will recognize external interrupt request except those that are
masked.
Instruction and assembly language Program

 MACHINE CONTROL INSTRUCTIONS:

2. DI (disable interrupts):
 The interrupt system is disabled immediately following the execution of the DI
instruction
 When this instruction is executed, then INTE F/F is reset so that all the interrupts are
disabled except TRAP and 8085 A will not recognize any external interrupt request.
Instruction and assembly language Program

 MACHINE CONTROL INSTRUCTIONS:

3. NOP (No operation):
 The meaning of the instruction is “No operation is performed”. The registers and flags
are unaffected.
Instruction and assembly language Program

 MACHINE CONTROL INSTRUCTIONS:

4. HLT: (Halt):
 When this instruction is executed the processor is stopped, i.e, it stops fetching and
executing instructions from the program memory.
Instruction and assembly language Program

 MACHINE CONTROL INSTRUCTIONS:

RIM & SIM:
 These instructions are dual purpose instructions and used both for interrupts mask
control and serial communication.
Instruction and assembly language Program

 MACHINE CONTROL INSTRUCTIONS:

5. SIM (Set interrupt mask):
 It operates on the contents of (A) before SIM is executed.
 It has no variation. The registers & flags are unaffected.
Instruction and assembly language Program
 MACHINE CONTROL INSTRUCTIONS:
5. SIM (Set interrupt mask):
 The format of accumulator for SIM instruction is
Instruction and assembly language Program
 MACHINE CONTROL INSTRUCTIONS:
5. SIM (Set interrupt mask):
 The SIM instruction uses the contents of the accumulation to perform the following functions:
 Program the interrupts mask for the RST 5.5, RST 6.5, & RST 7.5 hardware interrupts.
 The interrupts can be masked or unmasked by controlling A0, A1, & A2 bits of accumulator before
using SIM.
 If any bit is‟1‟, then the corresponding interrupt is masked i.e, these interrupts will not be
recognized.
 If any of these bits is „0‟, the corresponding interrupt is unmasked, i.e, if the corresponding
interrupt occurs, it will be acknowledged.
 These bits will affect the interrupts only if MSE (mask set enable) bit (A3) is also 1. If A3 is “0”,
when the SIM instruction is executed, the interrupt mask register is not changed.
Instruction and assembly language Program
 MACHINE CONTROL INSTRUCTIONS:
5. SIM (Set interrupt mask):
 RST 7.5 is edge sensitive interrupt (LOW HIGH).
 A pulse at the RST 7.5 always sets an internal R7.5 F/F even if the jump to the service routine
is inhibited by masking. If interrupts are disabled at the time the RST 7.5 pulse occurs, this
input will still be recognized later since the R7.5 F/F has already been SET by the pulse.
 This F/F can be cleared (or Reset) by keeping bit A4=1 when SIM is executed.
 This may be required if we do not want to service an earlier RST 7.5 interrupted.
 The R7.5 F/F is also cleared by a RESETIN signal input or when the CPU acknowledges a
RST 7.5 interrupt. All three mask bits (A2, A1, A0) are also set by R E S E T I N i.e, all
vectored interrupts (except TRAP) are masked and, therefore, disabled.
Instruction and assembly language Program

 MACHINE CONTROL INSTRUCTIONS:

5. SIM (Set interrupt mask):
 Load the SOD (serial output data) latch.
 The SOD output of the 8085A shows the status of a 1-bit output port.
 Execution of the SIM instruction sets the output port content to that of A7 provided the
serial output enable A6 is also 1. If SOE = A6=0, the contents of the output port is
unaffected SOD is reset by the RESETIN input.
Instruction and assembly language Program
 MACHINE CONTROL INSTRUCTIONS:
5. SIM (Set interrupt mask):
 (1) Send a “1” to the SOD output line. The following sequence of instruction shall do the
word.
MVI A, C0H (1100 0000)2
SIM
 (2) The following sequence of instruction shall unmask RST 6.5 interrupt control signal
input & mask all other interrupts after power on.
MVI A, 0DH (0000 1101)2
SIM
EI
Instruction and assembly language Program
 MACHINE CONTROL INSTRUCTIONS:
6. RIM (Read Interrupt Mask):
 Whenever this instruction is executed the status of the mask F/Fs, INTE F/F the SID input & of pending
interrupts is read into accumulation as follows.
Instruction and assembly language Program
 MACHINE CONTROL INSTRUCTIONS:
6. RIM (Read Interrupt Mask):
 The RIM instruction loads data into accumulation relating to interrupts & the serial input. After RIM is
executed the content of A are as follows:
 Current interrupt enables status for the RST 5.5, 6.5, 7.5 hardware interrupts in A0 A1 & A2 bits (1= if
masked/disabled or 0 if they are enabled).
 Current interrupt enable flag status in bit A3. (=1 interrupts enabled) except immediately following a
TRAP interrupt.
 Following a TRAP interrupt, IE = A3 reports the status of interrupts (enabled/d i s a b le d ) prior to the
TRAP interrupt.
 This is useful to retrieve current interrupt status following TRAP. This is important since TRAP is a non
maskable interrupt which can happen at any time.
Instruction and assembly language Program

 MACHINE CONTROL INSTRUCTIONS:

6. RIM (Read Interrupt Mask):
 Hardware pending interrupts (Interrupt received but not serviced). on the RST 7.5, RST 6.5 & RST 5.5
lines. A “1” at A6, A5, A4, respectively indicate that RST 7.5, 6.5 & 5.5 interrupts are pending.
 Transfer the bit present at 8085A‟s SID input to A7.
 Apart from the letting the CPU get the SID input, the RIM instruction is primarily used to monitor
interrupt status. e.g.
 a) Monitor whether or not an interrupt is pending without actually servicing it.
 b) Check using IE properly if CPU is currently, servicing an interrupt.
 c) By properly using RIM & SIM one can design any other priority structure.
MACHINE CYCLES OF 8085

 The 8085 microprocessor has 5 (seven) basic machine cycles. They are

1. Opcode fetch cycle (4T)

2. Memory read cycle (3 T)
3. Memory write cycle (3 T)
4. I/O read cycle (3 T)
5. I/O write cycle (3 T)
MACHINE CYCLES OF 8085

 MOV instruction:
MACHINE CYCLES OF 8085

 STA instruction: STA Y3Y2Y1Y0

Program Memory Location Machine Code

X3 X2 X1 X0 32H
X3X2X1X0+1 Y1Y0H
X3X2X1X0+2 Y3Y2H
MACHINE CYCLES OF 8085

 OUT instruction: OUT IOPORT

ADDRESSING MODES

 Addressing Modes:
 Most of the instruction execution requires two operands e.g. transfer of data between
two registers of a microprocessor system.
 How the 𝑝knows the positions of these operands? The method of identifying the
operands position by the instruction format is known as the addressing mode.
 Whenever two operands are involved in an instruction, the first operand is assumed to
be in any register of the 𝑝itself.
ADDRESSING MODES

 Addressing Modes:
1. Register Addressing Mode
2. Direct Addressing Mode
3. Register Indirect Addressing Mode
4. Immediate Addressing Mode
5. Implied Addressing Mode
ADDRESSING MODES

1. Register Addressing Mode:

 When the operands for any instruction are available in internal general purpose
registers, only the registers need be specified as the address of the operands.
 Such instruction are said to use the register addressing mode.
 For example, MOV r1, r2; ADD r; XCHG; DAD rp etc.
ADDRESSING MODES

2. Direct Addressing Mode:

 In this addressing mode, the instruction contains the address of the operand (external
register) involved in the transfer.
 The 8085A provides16-bit memory address requiring that the address contained in the
instruction be 16-bit long as a second and third bytes of the instruction.
 Thus it is invariably a 3-byte instruction.
 e.g. LDA addr.,
ADDRESSING MODES

3. Register Indirect Addressing Mode:

 In this case, the instruction specifies a register pair which contains the address of the
memory where the data is located or into which the data in to be placed.
 Thus the address of the operand is given indirectly through a register pair.
 i.e. LDAX rp and STAX rp, MOV r, M, ADD M.
ADDRESSING MODES

4. Immediate Addressing Mode:

 In this type of addressing mode, the operand is available directly in the instruction
itself.
 If the operand data involved is of 8-bits then the instruction is of two bytes. The first
byte is the opcode followed by 8-bit data byte.
 If 16-bit data is involved in the instruction then the first byte is opcode at memory
location N followed by the lower order data byte at memory location N+1 and higher
order data byte at memory location N+2.
 e.g. MVI r, data, LXI rp data,
ADDRESSING MODES

5. Implied Addressing Mode::

 There are certain instructions that operate on one operand.
 Such instructions assume that the operand is in the ACC and, therefore, need not
specify any address.
 Many instructions in the logical group like RLC, RRC, RAR, RAL and CMA fall in to
this category.
 All these are one byte instruction.
 Those instructions that specify the address of one operand, use implied addressing for
the other operand.
 Assignments
1. Explain T-state, Machine cycle and Instruction cycle. Draw timing diagram of OUT FFh
instruction
2. What is stack? Explain stack operations in 8085 microprocessor using PUSH and POP
instructions with neat sketches. When stack operations are needed?
3. STA instruction requires 5 machine cycles and 13T states. Explain using timing diagram
sequence of events taking place in each machine cycle with reference to 3000H
……………STA 4000H instruction.
4. Write interrupt vector table for vectored interrupts.
5. Explain SIM and RIM instructions.
6. Draw and explain timing diagram of STA 5000H instruction of 8085.
7. Draw and explain timing diagram of MOV A,B instruction of 8085.
Thank you…