CHAPTER 3

BASIC COMPUTER ORGANISATION AND

DESIGN
LH- 8 Hours
Prepared By: Rolisha Sthapit
CONTENTS
3.1 Basic Concepts: Instruction Code, Operation Code, Concept of
Instruction Format, Stored Program Concept.
3.2 Basic Computer Registers and Memory: List of Registers, Memory
of Basic Computer, Common Bus System for Basic Computer.
3.3 Basic Computer Instructions: Instruction Format, Instruction Set
Completeness, Control Unit of Basic Computer, Control Timing Signals
3.4 Instruction Cycle of Basic Computer: Fetch and Decode,
Determining Type of Instruction, Memory Reference Instructions, Input-
Output Instructions, IO Interrupt, Program Interrupt, Interrupt Cycle.
3.5 Description and Flowchart of Basic Computer
INTRODUCTION: Description of
Basic Computer
• We introduce here a basic computer whose operation can be specified
by the register transfer statements. Internal organization of the
computer is defined by the sequence of microoperations it performs on
data stored in its registers. Every different processor type has its own
design (different registers, buses, microoperations, machine instructions,
etc). Modern processor is a very complex device. It contains:
– Many registers
– Multiple arithmetic units, for both integer and floating point
calculations
– The ability to pipeline several consecutive instructions for execution
speedup
Continue
• However, to understand how processors work, we will start with a
simplified processor model. M. Morris Mano introduces a simple
processor model; he calls it a ―Basic Computer. The Basic Computer
has two components, a processor and memory.
• The memory has 4096 words in it
–4096 = 212, so it takes 12 bits to select an address in memory
• Each word is 16 bits long
3.1 Instruction Code and Stored
Program Organisation
• An instruction code is a group of bits that instructs the computer to
perform a specific operation. It is usually divided into parts each having
one particular interpretation. Most basic part is operation (operation
code).
• Operation code is group of bits that defines operations as add, subtract,
multiply, shift, complement etc. The operation part of an instruction code
specifies the operation to be performed. This operation must be
performed on some data stored in processor register or in memory.
• An instruction code therefore specify not only the operation but also the
register or the memory word where the operand (data on which
operation is performed) are to be found.
Stored Program Organization:
• The program (instruction) as well as data (operand) is stored in the same
memory. If the instruction needs data, the data is found in the same memory and
accessed. This feature is called stored program organization.
Instruction Formats
Instruction Format of Basic Computer:
A computer instruction is often divided into two parts
– An opcode (Operation Code) that specifies the operation for that instruction
– An address that specifies the registers and/or locations in memory to use for
that operation.
In the Basic Computer, since the memory contains 4096 (= 212) words, we needs 12
bit to specify the memory address that is used by this instruction. In the Basic
Computer, bit 15 of the instruction specifies the addressing mode (0: direct
addressing, 1: indirect addressing). Since the memory words, and hence the
instructions, are 16 bits long, that leaves 3 bits for the instruction’s opcode.
Addressing Modes:
Addressing Modes:
The address field of an instruction can be represented in two ways
– Direct address: the address operand field is effective address (the
address of the operand)
– Indirect address: the address in operand field contains the memory
address where effective address resides.
Note: Effective Address (EA): The address, where actual data resides is
called effective address.
Continue:
Continue
• A direct address instruction is shown in figure b. It is placed in address 22 in
memory. The I bit is 0, so the instruction is recognized as a direct address
instruction. The opcode specifies an ADD instruction, and the address part is the
binary equivalent of 457. The control finds the operand in the memory at address
457 and adds it to the content of AC.
• The instruction in address 35 shown in figure c has a mode bit I=1. Therefore, it is
recognized as indirect address instruction. The address part is the binary equivalent
of 300. The control goes to address 300 to find the address of an operand. The
address of an operand in this case is 1350. The operand found in address 1350 is
then added to the content of AC. The indirect address instruction needs two
references to memory to fetch an operand. The first reference is needed to read the
address of the operand and second is for the operand itself. The effective address of
direct addressing mode is 457 and that of indirect addressing mode is 1350.
3.2 Computer Registers
• Computer instructions are normally stored in the consecutive
memory locations and are executed sequentially one at a time. Thus
computer needs processor registers for manipulating data and
holding memory address which are shown in the following table:
Symbol Size Register Name Description
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
• Since the memory in the Basic Computer only has 4096 (=212) locations, PC and
AR only needs 12 bits. Since the word size of Basic Computer only has 16 bit, the
DR, AC, IR and TR needs 16 bits. The Basic Computer uses a very simple model of
input/output (I/O) operations.
–Input devices are considered to send 8 bits of character data to the processor
–The processor can send 8 bits of character data to output devices
The Input Register (INPR) holds an 8-bit character gotten from an input device and
the Output Register (OUTR) holds an 8-bit character to be sent to an output device.
Q) Why the address bus (AR) and PC of basic computer is 12 bit?
Q) What is the use of PC?
Common Bus System
• The basic computer has eight registers, a memory unit, and a control
unit. These registers, memory and control unit are connected using a
path (bus) so that information can be transferred to each other. If
separate buses are used for connecting each registers, it will cost
high. The cost and use of extra buses can be reduced using a special
scheme in which many registers use a common bus, called common
bus system
Continue….
S2 S1 S0 Register
• The registers in the Basic
Computer are connected 0 0 0 X (nothing)
using a bus.
0 0 1 AR
• This gives a savings in circuitry
over complete connections 0 1 0 PC
between registers.
0 1 1 DR
• Three control lines, S2, S1,
and S0 control which register 1 0 0 AC

the bus selects as its input. 1 0 1 IR

1 1 0 TR

1 1 1 Memory
• The particular register whose LD (Load) input is enabled receives the data from the bus
during the next clock pulse transition. The memory receives the contents of the bus when
its write input is activated.
• The memory places its 16 bit output onto the bus when the read input is activated and
the value of S2, S1, and S0 is 111.
• Four registers DR, AC, IR and TR have 16 bits each and two registers AR and PC have 12
bits each since they hold a memory address.
• When the content of AR and PC are applied to the 16-bit common bus, the four MSBs are
set to 0’s.
• When AR and PC receive information from the bus, only the 12 least significant bits are
transferred into the register.
• The input register INPR and the output register OUTR have 8 bits each and communicate
with the eight least significant bits in the bus.
• INPR is connected to provide information to the bus but OUTR can only receive
information from the bus.
• Five registers have three control inputs: LD (load), INR (increment) and
CLR(Clear).
• Two registers have only a LD input.
• AR must always be used to specify memory address; therefore memory
address is connected to AR. The 16 inputs of AC come from an Adder and Logic
Circuit. This circuit has three inputs.
• Set of 16- bit inputs come from the outputs of AC.
• Set of 16-bit inputs come from the data register DR.
• Set of 8-bit inputs come from the input register INPR.
• The result of an addition is transferred to AC and the end carry out of
the addition is transferred to flip flop E (extended AC-bit).
• The clock transition at the end of the cycle transfers the content of
the bus into the designated destination register and the output of the
adder and logic circuit into AC.
3.3 Basic Computer Instructions
The basic computer has 3 instruction code formats. Type of the
instruction is recognized by the computer control from 4-bit positions
12 through 15 of the instruction.
• Memory-Reference Instructions
• Register-Reference Instructions
• Input-Output Instructions
1. Memory-Reference Instructions:
2. Register-Reference Instructions
3. Input-Output Instructions
Instruction Set Completeness
An instruction set is said to be complete if it contains sufficient instructions to perform operations in
following categories:
Functional Instructions
• Arithmetic, logic, and shift instructions
• Examples: ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
• Data transfers between the main memory and the processor registers
• Examples: LDA, STA
Control Instructions
• Program sequencing and control
• Examples: BUN, BSA, ISZ
Input/output Instructions
• Input and output
• Examples: INP, OUT
Instruction set of Basic computer is complete because:
• ADD, CMA (complement), INC can be used to perform addition and subtraction
and CIR (circular right shift), CIL (circular left shift) instructions can be used to
achieve any kind of shift operations. Addition subtraction and shifting can be used
together to achieve multiplication and division. AND, CMA and CLA (clear
accumulator) can be used to achieve any logical operations.
• LDA instruction moves data from memory to register and STA instruction moves
data from register to memory.
• The branch instructions BUN, BSA and ISZ together with skip instruction provide
the mechanism of program control and sequencing.
• INP instruction is used to read data from input device and OUT instruction is used
to send data from processor to output device.
3.3Timing and Control Unit
Control Unit
Control unit (CU) of a processor translates from machine instructions to the control
signals for the microoperations that implement them. There are two types of control
organization:
a) Hardwired Control
b) Microprogrammed Control
a) Hardwired Control
CU is made up of sequential and combinational circuits to generate the control signals.
If logic is changed, we need to change the whole circuit.
Expensive
Fast
b) Microprogrammed Control
A control memory on the processor contains microprograms that
activate the necessary control signals.
If logic is changed, we only need to change the microprogram.
Cheap
Slow
Control Unit of a Basic
Computer (Hardwired Control)
The block diagram of a hardwired control unit is shown below. It
consists of two decoders, a sequence counter, and a number of control
logic gates.
Timing Signal
• Generated by 4-bit sequence counter and 4x16 decoder.
• The SC can be incremented or cleared.
• Example: T0, T1, T2, T3, T4, T0, T1 . . .
• Assume: At time T4, SC is cleared to 0 if decoder output D3 is active:
• D3T4: SC 0
3.5 Instruction Cycle of Basic
Computer
Processing required for complete execution of an instruction is called instruction cycle.
In Basic Computer, a machine instruction is executed in the following cycle:
• Fetch an instruction from memory
• Decode the instruction
• Read the effective address from memory if the instruction has an indirect
address
• Execute the instruction
• Upon the completion of step 4, control goes back to step 1 to fetch,
decode and execute the next instruction. This process is continued
indefinitely until HALT instruction is encountered.
Fetch and Decode
Sequence of steps required for fetching instruction from memory to
CPU internal register is known as fetch cycle. The microoperations for
the fetch and decode phases can be specified by the following resister
transfer statements: (first two steps for fetch and third step for decode)
• Determine the type of the instruction
The timing signal that is active after decoding is T3. During time T3, the
control unit determines the type of instruction that was just read from
memory. Following flowchart presents an initial configuration for the
instruction cycle and shows how the control determines the instruction
type after decoding.
Then, among decoded, D7 determines which type of instruction.
1) If D7 = 1, it will be either register-reference or input-output
instruction.
If I = 1, input-output instruction is executed during T3.
If I = 0, register-reference instruction is executed during T3.
2) If D7 = 0, it will be memory-reference instruction.
If I = 1, indirect addressing mode instruction during T3.
If I = 0, direct addressing mode instruction during T3.
The SC is reset after executing each instruction.
Register-Reference Instructions
Register Reference Instructions are identified when
• - D7 = 1, I = 0
• - Register Ref. Instr. is specified in b0 ~ b11 of IR
• - Execution starts with timing signal T3
• Let r = D7 I’T3 => Common to all Register Reference Instruction
• Bi = IR (i), i=0, 1, 2... 11. [Bit in IR(0-11) that specifies the operation]
Memory-reference instructions

• Once an instruction has been loaded to IR, it may require further access to
memory to perform its intended function (direct or indirect).
• The effective address of the instruction is in the AR and was placed their
during:
- Time signal T2 when I = 0 or
- Time signal T3 when I = 1
• Execution of memory reference instructions starts with the timing signal
T4.
•  Described symbolically using RTL.
Input-Output Configuration
The terminal sends and receives serial information. Each quantity of
information has 8 bits of an alphanumeric code. The serial information
from the keyboard is shifted into the input register INPR. The serial
information for the printer is stored in the output register OUTR. These
two registers communicate with a communication interface serially and
with the AC in parallel. The input—output configuration is shown in
figure. The transmitter interface receives serial information from the
keyboard and transmits it to INPR. The receiver interface receives
information from OUTR and sends it to the printer serially.
Scenario1: when a key is struck in the keyboard, an 8-bit alphanumeric
code is shifted into INPR and the input flag FGI is set to 1. As long as the
flag is set, the information in INPR cannot be changed by striking another
key. The control checks the flag bit, if 1, contents of INPR is transferred in
parallel to AC and FGI is cleared to 0. Once the flag is cleared, new
information can be shifted into INPR by striking another key.
Scenario2: OUTR works similarly but the direction of information flow is
reversed. Initially FGO is set to 1. The computer checks the flag bit; if it is 1,
the information is transferred in parallel to OUTR and FGO is cleared to 0.
The output device accepts the coded information, prints the corresponding
character and when operation is completed, it sets FGO to 1.
Input-output Instructions : I/O instructions are needed to transferring
information to and form AC register, for checking the flag bits and for
controlling the interrupt facility.
Program Interrupt
• Input and Output interactions with electromechanical peripheral devices
require huge processing times compared with CPU processing times – I/O
(milliseconds) versus CPU (nano/micro-seconds)
• Interrupts permit other CPU instructions to execute while waiting for I/O to
complete
• The I/O interface, instead of the CPU, monitors the I/O device.
• When the interface founds that the I/O device is ready for data transfer, it
generates an interrupt request to the CPU
• Upon detecting an interrupt, the CPU stops momentarily the task it is
doing, branches to the service routine to process the data transfer, and
then returns to the task it was performing.
Description
• The flowchart consists of R – an interrupt flip flop where if R=0 it proceeds to
instruction cycle and if R=1, it proceeds to interrupt cycle.
• When R=0, the computer goes through an instruction cycle. During the
execution phase of the instruction cycle, IEN (Interrupt enable flip flop) is
checked by the control. If it is 0, it indicates that the programmer does not
want to use the interrupt so control continues with the next instruction
cycle. If IEN= 1, control checks the flag bit, If both flags are 0, it indicates that
neither the input nor the output registers are ready for the transfer of
information. In this case, control continues with the next instruction cycle. If
either flag is set to 1 while IEN=1, flip flop R is set to 1. At the end of the
execute phase, control checks the value of R, and if it is equal to 1, it goes to
an interrupt cycle instead of an instruction cycle.
Continue…..
• When R=1, the interrupt instruction executes the following steps:
a) Save the current program and return to the interrupt where PC
proceed to zero memory.
M[0] PC
b) Control then issues address 1 into PC.
c) Finally, interrupt is finished or cleared then IEN=0, R=0, further
proceed to instruction cycle.
Register Transfer in Interrupt Cycle
 Design of Basic Computer
The basic computer consists of the following hardware components:
A memory unit with 4096 words of 16 bits each.
Nine registers: AR(Address Reg.), PC (Program Counter), DR(Data Reg.), AC
(Accumulator), IR (Instruction Reg.), TR (Temp. Reg.),
OUTR (Output Reg.), INPR (Input Reg.), and SC (Sequence Counter).
Flip-flops: IEN (Interrupt Enable), FGI (Input Flag), and FGO (Output Flag).
Two decoders: a 3 x 8 operation decoder and a 4 x 16 timing decoder
A 16-bit common bus.
Control logic gates.
Adder and logic circuit connected to the input of AC.
Control Functions and Microoperations of
Basic Computer
 Design of Accumulator Logic

• The circuits associated with the AC register are

shown in Fig. The adder and logic circuit has
three sets of inputs.
• One set of 16 inputs comes from the outputs of
AC.
• Another set of 16 inputs comes from the data
register DR.
• A third set of eight inputs comes from the input
register INPR.
• The outputs of the adder and logic circuit
provide the data inputs for the register. In
addition, it is necessary to include logic gates for
controlling the LD, INR, and CLR in the register
and for controlling the operation of the adder
and logic circuit.
 Control of AC Register – Gate Structure
• The gate structure that controls the LD, INR, and
CLR inputs of AC is shown in Fig.
• The output of the AND gate that generates this
control function is connected to the CLR input of
the register.
• Similarly, the output of the gate that implements the
increment micro operation is connected to the INR
input of the register.
• The other seven micro operations are generated in
the adder and logic circuit and are loaded into AC at
the proper time.
• The outputs of the gates for each control function is
marked with a symbolic name. These outputs are
used in the design of the adder and logic circuit.
 Adder and Logic Circuit

The adder and logic circuit can be

sub-divided into 16 stages with
each stage corresponding to one bit
of AC. The load (LD) input is
connected to the inputs of the AND
gate.