Digital Logic-Lesson2
Digital Logic-Lesson2
LOGICS
IFT211/CSC
212
DR. ABIODUN AND MR. OLOWE
OBJECTIVES
At the end of this unit, student should be able to:
· identify the different logic gates
· analyze circuits with logic gates
· generate other gates from the universal gates.
LOGIC GATES
Logic Gates may be defined as the digital circuits capable of performing a
particular logic function by operating on a number of binary inputs. OR Logic
gates are the basic building blocks of any digital circuit.
Basic logic gates are associative in nature. (It states that the order in
that changing the sequence of the variables does not have any effect
on the output of a logic circuit.)
The three basic logic gates are-
AND Gate
OR Gate
NOT Gate
DIFFERENT
REPRESENTATION OF
GATES
Logic gates can be represented using different
methods among which are:
1. Symbol
2. Truth Table
3. Timing Diagram
4. Boolean Algebra
SYMBOL: AND Gate
The output of AND gate is high (‘1’) if all of its inputs are high (‘1’).
The output of AND gate is low (‘0’) if any one of its inputs is low (‘0’).
AND LOGIC SYMBOL
TRUTH TABLE
A B Y = A.B
0 0 0
0 1 0
1 0 0
1 1 1
TIMING DIAGRAM
A timing diagram is a graph of the output of a logic gate with
respect to the inputs of the gate. A timing diagram plots
voltage (vertical) with respect to time (horizontal). A timing can
also be seen as waveforms on an oscilloscope or on a logic
analyzer
BOOLEAN ALGEBRA
Boolean algebra is the category of algebra in which the variable’s values are
the truth values, true and false, ordinarily denoted 1 and 0 respectively. It
is used to analyze and simplify digital circuits or digital gates. It is also
called Binary Algebra or logical Algebra. It has been fundamental in the
development of digital electronics and is provided for in all modern
programming languages. It is also used in set theory and statistics.
The output of OR gate is high (‘1’) if any one of its inputs is high (‘1’).
The output of OR gate is low (‘0’) if all of its inputs are low (‘0’).
The logic symbol for OR Gate is as shown below-
TRUTH TABLE FOR OR GATE
A B Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1
TIMING DIAGRAM FOR OR GATE
A B Y=A+B
0 0 1
0 1 0
1 0 0
1 1 0
NOR GATE TIMING
DIAGRAM
NAND Gate-
A NAND Gate is constructed by connecting a NOT
Gate at the output terminal of the AND Gate.
The output of NAND gate is high (‘1’) if at least one
of its inputs is low (‘0’).
The output of NAND gate is low (‘0’) if all of its
inputs are high (‘1’).
CLASS WORK
A B Y
0 0 0
0 1 1
BOOLEAN ALGEBRA Y = (AB)
1 0 1
1 1 0
OTHER GATES
EXNOR GATE
EXNOR obeys the definition, the output of a two input exclusive
NOR assumes the logic ‘1’ state (true) if and only if the two inputs
are similar. It is an important gate for it can only have two inputs at
a time.
A B Y
0 0 1
0 1 0
BOOLEAN ALGEBRA Y = (AB)
1 0 0
1 1 1
OUTPUTS OF SIX
DIFFERENT GATES
INPUTS
OUTPUTS
A
B
C
D
D
Determining outputs value from a
Diagram
A
B
C
(i) X = 0
(ii) X = 0
(iii) X = 1
(iv) (A’.B.C). (A+D)’ = (A.B.C).(A+D) = PQ
Transform a circuit into a
truth table
A P
C Q
CIRCUITS TO TRUTH
TABLE
X Q
Z R
P
CIRCUITS TO TRUTH
TABLE