Computer

Architecture

AS and A level Computer

Science
 Course Objective

• Students will learn about:

• Describe the interaction of CPU with peripheral
devices
• Describe the purpose of CPU components, system bus
and main memory
 Main Menu

Lessons Activities Resources

Lessons
Introduction
• Very early computers could not save programs; as a
result, in 1945, John von Neumann created the von
Neumann architecture, a design for a computer that
could do so.
• He proposed that information and software might be
kept in memory, and that information would be moved
from memory to processor during processing.
 Components of a Computer (IPOS)
• Input – Receives information and instructions gives it to the
computer
• Memory – Stores received information and instructions
temporarily
• Processor – Process information using ALU and CU
• Output – displays processed information
• Storage – Stores processed information permanently
Components of a Computer (IPOS)
 Memory

• Purpose: RAM provides fast and temporary storage for data

and instructions that the CPU is currently using.
• Function: RAM allows the CPU to quickly access and
manipulate data during program execution. It stores data and
program code that are actively being used, and its contents
are volatile, meaning they are lost when the computer is
powered down.
 Output Devices

• Purpose: Output devices are responsible for presenting

processed data and results to the user in a human-readable
format.
• Function: Output devices can include monitors, printers,
speakers, and displays. They convert machine-readable data
into human-readable information.
 Input Devices

• Purpose: Input devices are used to enter data and

instructions into the computer system.
• Function: Input devices can include peripherals like
keyboards, mice, touchscreens, and scanners. They convert
human-readable data and commands into a format that the
computer can understand and process.
 Processor

• Purpose: The CPU is the "brain" of the computer, responsible

for executing instructions and performing calculations.
• Function: The CPU fetches instructions and data from
memory, decodes the instructions, executes them, and then
stores the results back in memory or sends them to output
devices. It performs arithmetic and logical operations and
controls the overall operation of the computer.
Von Neumann Architecture

• The Von Neumann architecture displays a

detailed computer interaction. It displays how
the processor, memory, and input/output
devices are connected. These links are known as
busses. The address bus, control bus, and data
bus are three distinct bus types.
 Control Unit

ALU
Input
Registers Output
Device PC
Devices
s
CIR ACC MAR MDR

Memory Unit
 Purpose: To provide a means for
users to input data and instructions
into the computer system.
Input
Device Function: Input devices like
s keyboards, mice, and scanners
convert user input into a format that
can be processed by the computer.
 Control Unit

ALU
Input
Registers Output
Device PC
Devices
s
CIR ACC MAR MDR

Memory Unit
 Purpose: To present processed data
and results to the user in a human-
readable format.
Output
Function: Output devices like
Devices
monitors, printers, and speakers
convert machine-readable data into
a format that users can understand.
 Control Unit

ALU
Input
Registers Output
Device PC
Devices
s
CIR ACC MAR MDR

Memory Unit
 Control Unit

Purpose: To manage and coordinate the

activities of various components within the
computer.
Function: The CU controls the flow of data and
instructions within the computer. It fetches
instructions from memory, decodes them, and
issues control signals to the ALU, memory
 Control Unit

ALU
Input
Registers Output
Device PC
Devices
s
CIR ACC MAR MDR

Memory Unit
 ALU

Purpose: To perform arithmetic and logical

operations on data.
Function: The ALU executes mathematical
calculations (e.g., addition, subtraction) and
logical operations (e.g., AND, OR) as directed
by the CPU's instructions.
 Control Unit

ALU
Input
Registers Output
Device PC
Devices
s
CIR ACC MAR MDR

Memory Unit
 Memory Unit

Purpose: To provide fast and temporary

storage for data and instructions that the
CPU is actively using.
Function: RAM allows the CPU to quickly
access and manipulate data during program
execution. It stores data and program code
in a volatile form.
 Control Unit

ALU
Input
Registers Output
Device PC
Devices
s
CIR ACC MAR MDR

Memory Unit
 Purpose: To store data that the
CPU is actively working with
during computations.
Function: These registers are
Registers
PC
used for various temporary data
CIR ACC MAR MDR storage and manipulation tasks.
They are frequently used for
arithmetic, logical operations,
and holding intermediate results.
 Purpose: To keep track of the
memory address of the next
instruction to be fetched and
executed.

PC Function: The PC holds the address of

the instruction currently being
executed and is automatically
incremented to point to the next
instruction in memory after each
instruction is fetched.
 Purpose: To temporarily store the
current instruction being executed.
Function: The IR holds the
instruction that has been fetched
CIR from memory and is currently being
executed by the CPU. The control
unit (CU) decodes and executes the
instruction based on its contents.
 Purpose: The accumulator is a special-
purpose register within the CPU that is
primarily used for performing arithmetic
and logical operations.

ACC Function: During the execution of an

instruction, the accumulator temporarily
stores the results of intermediate
calculations. For example, in an addition
operation, the accumulator holds the sum
of the operands.
 Purpose: The MAR is a special register within the
CPU that holds the memory address of the data
or instruction to be read from or written to in the
computer's memory.

Function: When the CPU needs to access data or

MAR instructions from memory, it loads the memory
address into the MAR. The MAR specifies the
location in memory where the data is located or
where it should be stored. It helps in addressing
specific locations within the memory hierarchy,
ensuring that the CPU interacts with the correct
memory location.
 Purpose: The MDR is another specialized register
within the CPU that temporarily holds the data
that has been read from memory or is about to
be written to memory.

Function: When the CPU retrieves data from

MDR memory, that data is temporarily stored in the
MDR before it can be processed further. Similarly,
when the CPU needs to write data to memory, it
places the data into the MDR before sending it to
the memory unit for storage. Essentially, the
MDR acts as a buffer between the CPU and the
memory, facilitating data transfer.
Busses
In a CPU architecture, there are several buses (pronounced
"busses") that play a crucial role in facilitating data and
control signal transfer between various components of the
computer. These buses are pathways or sets of wires that
connect different parts of the CPU and other components
within the computer system. The three primary types of
buses in a CPU architecture are the data bus, address bus,
and control bus.
 Memory unit
MAR MDR

ALU

Input devices Processor Output Devices

ACC

Processor Control Unit PC CIR

 Memory unit
MAR MDR

ALU

Input devices Processor Output Devices

ACC

Processor Control Unit PC CIR

 Memory unit
MAR MDR

Control
Bus
ALU

Input devices Processor Output Devices

ACC

Control Control
Control
Bus Bus
Bus

Control
Processor Control Unit PC CIR
Bus
Control Bus
Purpose: The control bus carries various control signals that
coordinate and manage the operations of the CPU and other
components.
Function: Control signals on the control bus include commands
to read from or write to memory, signals to indicate whether
data transfer is a read or write operation, clock signals for
synchronization, and signals for interrupt requests and other
control functions. These signals help orchestrate the various
activities within the CPU and across the computer system.
 Memory unit
MAR MDR

ALU

Input devices Processor Output Devices

ACC

Processor Control Unit PC CIR

 Data bus Memory unit
MAR MDR

Data bus
Data bus

ALU

Input devices Processor Output Devices

ACC

Processor Control Unit PC CIR

Data Bus
Purpose: The data bus is responsible for carrying data
between the CPU and memory, as well as between the CPU
and other peripheral devices.
Function: When the CPU needs to read data from memory
or write data to memory or I/O devices, the data is
transferred over the data bus. The width of the data bus,
measured in bits (e.g., 8-bit, 16-bit, 32-bit, 64-bit),
determines how much data can be transferred in a single
bus operation.
 Memory unit
MAR MDR

ALU

Input devices Processor Output Devices

ACC

Processor Control Unit PC CIR

 Memory unit
MAR MDR

ALU

Input devices Processor Output Devices

ACC

Processor Control Unit PC CIR

 Memory unit
MAR MDR

ALU

Input devices Processor Output Devices

ACC

Address bus

Processor Control Unit PC CIR

Address Bus
Purpose: The address bus is used to specify the memory
location (address) from which data should be read or to which
data should be written.
Function: The CPU places the memory address it wants to
access on the address bus. The width of the address bus
determines the maximum addressable memory space, which
is typically expressed as 2^n, where n is the number of bits in
the address bus. For example, a 16-bit address bus can
address up to 65,536 memory locations.
 Memory unit
MAR MDR

Control Bus Data bus

ALU

Input devices Processor Output Devices

ACC

Address bus

Processor Control Unit PC CIR

Registers
Registers
Registers are important components within a
computer's central processing unit (CPU) in the
Von Neumann architecture. Think of registers
as small efficient memory units inside the CPU
that stores specific Information/Data
Registers

CPU
Registers

CPU
Registers
Control Unit

Arithmetic and Logic Unit

Registers
Registers

Registers
Registers
CIR

ACC Registers PC

MDR MAR
Registers
Accumulator (ACC):
ACC Definition: The Accumulator is a special-purpose
register within the CPU.
Function: The ACC temporarily stores the results
of intermediate arithmetic and logical
operations. It's frequently used for accumulating
results, especially during multi-step calculations.
The ACC holds the output of operations
performed by the ALU and can serve as a source
or destination for data during calculations.
Registers
Program Counter (PC):
PC
ACC
Definition: The Program Counter is a special
register within the CPU that keeps track of the
memory address of the next instruction to be
executed.
Function: The PC is automatically incremented after
each instruction is fetched, ensuring that the CPU
knows where to fetch the next instruction in
memory. It plays a vital role in controlling the flow
of program execution.
Registers
Current Instruction Register (CIR):
CIR
PC
ACC
Definition: The Current Instruction Register is a
temporary register within the CPU.
Function: The CIR holds the instruction that has
just been fetched from memory. It acts as a
holding ground for the instruction, allowing the
control unit to decode and execute it. The CIR
helps the CPU process instructions step by
step.
Registers
Memory Address Register (MAR):
CIR
PC
MAR
ACC
Definition: The Memory Address Register is a
register within the CPU that holds the memory
address of the data or instruction currently being
read from or written to in the computer's main
memory.
Function: The CPU uses the MAR to specify the
location in memory from which it wants to read
data or to which it wants to write data. It helps in
addressing specific memory locations.
Registers
Memory Buffer/Data Register (MBR/MDR):
CIR
PC
MDR
MAR
ACC
Definition: The Memory Buffer Register is a two-way
register within the CPU that serves as an intermediary
between the CPU and memory.
Function: When data is fetched from memory, it is
temporarily stored in the MBR before the CPU can
process it. Similarly, when the CPU wants to write data
to memory, it places the data into the MBR before it's
transferred to memory. The MBR acts as a buffer
during data transfer between the CPU and memory.
Registers
CIR

ACC Registers PC

MDR MAR
Detailed Von
Neumann
Architecture
 Memory unit
MAR MDR

Control Bus Data bus

ALU

Input devices Processor Output Devices

ACC

Address bus

Processor Control Unit PC CIR

Memory Unit
 Memory Unit
• Memory consist of partitions
• Each partition consist of a Address and Data
• Address uniquely identifies the contents of the data
Address Data
11001110 11001100
s
Partition
Memory

11001111 11001101
11011111 11001110
10011101 11001111
10011011 11001011
 Write Operation
1.Data Preparation: First, the CPU prepares the data that it wants to write into memory. This data could be
instructions, variables, or any other information that needs to be stored.

2.Memory Address Specification: The CPU needs to specify the memory address where it wants to write the data.
This address is typically stored in a register called the Memory Address Register (MAR). The CPU loads the desired
memory address into the MAR. For example, if you want to write data to address 11010000, you load this address
into the MAR.

3.Data Transfer: The CPU then places the data that it wants to write into memory into another register known as
the Memory Data Register (MDR). This is where the actual data to be written is temporarily stored.

4.Write Signal: The CPU sends a write signal to the memory unit, indicating that it wants to write data into the
specified memory address.

5.Data Transfer to Memory: When the memory unit receives the write signal, it retrieves the data from the MDR
(Memory Data Register) and writes it into the memory location specified by the address stored in the MAR (Memory
Address Register). In this case, it writes the data into the address 11010000.

6.Completion: Once the data has been successfully written to memory, the CPU can continue with its operations
Address Dataor
execute subsequent instructions as needed. 11001110 11001100
11001111 11001101
11011111 11001110
10011101 11001111
10011011 11001011
 Read Operation
1. Memory Address Specification: The CPU needs to specify the memory address from which it wants to read data.
This address is typically stored in a register called the Memory Address Register (MAR). The CPU loads the desired
memory address into the MAR. For example, if you want to read data from address 11010000, you load this address
into the MAR.

2. Read Signal: The CPU sends a read signal to the memory unit, indicating that it wants to retrieve data from the
specified memory address.

3. Data Retrieval: When the memory unit receives the read signal, it looks up the memory location specified by the
address stored in the MAR (Memory Address Register), which in this case is 11010000. It retrieves the data stored at
that memory address.

4. Data Transfer to CPU: The data retrieved from memory is transferred to a register called the Memory Data
Register (MDR). This is where the data is temporarily stored before it is sent to the CPU.

5. Data Availability: The CPU can now access the data from the MDR for further processing or execution of
instructions. It may perform operations on the retrieved data or use it as needed in the program.

6. Completion: Once the data has been successfully read from memory and placed in the MDR, Address
the CPU can continue
Data
with its operations or execute subsequent instructions as required. 11001110 11001100
11001111 11001101
11011111 11001110
10011101 11001111
10011011 11001011
Processor
 Data Bus
Address Bus

MAR MDR

PC
CIR

Control
Control Unit
Bus
Other
Registers
Arithmetic
and logic
unit
The fetch-decode-execute cycle
The fetch-decode-execute cycle is the process where the CPU
receives data and instructions from the RAM to the Memory
Unit, decodes the instructions and executes

Register transfer notation

Operations involving registers can be described by register
transfer notation. A simple example of this is a representation
of the fetch stage of the fetch–execute cycle:
MAR ← [PC]
PC ← [PC] + 1; MDR ← [[MAR]]
CIR ← [MDR]
 THE
FETCH-EXECUTE
CYCLE
Program 1
 REGISTERS
ACC
Check for Fetch
interrupts instruction
MBR
from memory
MAR 1

Execute CIR
Update
instruction Program PC 1
counter
MEMORY
Location Contents THE PROGRAM
The address of
23 14 the first 1 LDA 23
instruction is
53 26 2 ADD 72
copied from the
72 35 PC to the MAR 3 STA 53
 REGISTERS
ACC
Check for Fetch
interrupts instruction
MBR LDA 23
from memory
MAR 1

Execute CIR
Update
instruction Program PC 1
counter
MEMORY
Location Contents THE PROGRAM
The first
23 14 instruction is 1 LDA 23
read into the
53 26 2 ADD 72
MBR
72 35 3 STA 53
 REGISTERS
ACC
Check for Fetch
interrupts instruction
MBR LDA 23
from memory
MAR 1

Execute CIR LDA 23

Update
instruction Program PC 1
counter
MEMORY
Location Contents THE PROGRAM
The first
23 14 instruction is 1 LDA 23
copied into the
53 26 2 ADD 72
CIR
72 35 3 STA 53
 REGISTERS
ACC
Check for Fetch
interrupts instruction
MBR LDA 23
from memory
MAR 1

Execute CIR LDA 23

Update
instruction Program PC 2
counter
MEMORY
Location Contents THE PROGRAM
The program
23 14 counter is 1 LDA 23
updated to point
53 26 2 ADD 72
to the next
72 35 instruction 3 STA 53
 REGISTERS
ACC
Check for Fetch
interrupts instruction
MBR LDA 23
from memory
MAR 23

Execute CIR LDA 23

Update
instruction Program PC 2
counter
MEMORY
Location Contents THE PROGRAM
The address part
23 14 of the current 1 LDA 23
instruction is
53 26 2 ADD 72
placed in the
72 35 MAR 3 STA 53
 REGISTERS
ACC
Check for Fetch
interrupts instruction
MBR 14
from memory
MAR 23

Execute CIR LDA 23

Update
instruction Program PC 2
counter
MEMORY
The contents of THE PROGRAM
Location Contents the location
whose address 1 LDA 23
23 14
is in the MAR are
53 26 2 ADD 72
loaded into the
72 35 MBR 3 STA 53
 REGISTERS
ACC 14
Check for Fetch
interrupts instruction
MBR 14
from memory
MAR 23

Execute CIR LDA 23

Update
instruction Program PC 2
counter
MEMORY
Location Contents THE PROGRAM
The contents of 1 LDA 23
23 14
the MBR are
53 26 copied into the 2 ADD 72
72 35 ACC 3 STA 53
 REGISTERS
ACC 14
Check for Fetch
interrupts instruction
MBR 14
from memory
MAR 23

Execute CIR LDA 23

Update
instruction Program PC 2
counter
MEMORY
Location Contents THE PROGRAM
The Status 1 LDA 23
23 14
Register is
53 26 checked for 2 ADD 72
72 35 interrupts 3 STA 53
 REGISTERS
ACC 14
Check for Fetch
interrupts instruction
MBR 14
from memory
MAR 2

Execute CIR LDA 23

Update
instruction Program PC 2
counter
MEMORY
Location Contents THE PROGRAM
The address of
23 14 the second 1 LDA 23
instruction is
53 26 2 ADD 72
copied from the
72 35 PC to the MAR 3 STA 53
 REGISTERS
ACC 14
Check for Fetch
interrupts instruction
MBR ADD 72
from memory
MAR 2

Execute CIR LDA 23

Update
instruction Program PC 2
counter
MEMORY
Location Contents THE PROGRAM
The second
23 14 instruction is 1 LDA 23
read into the
53 26 2 ADD 72
MBR
72 35 3 STA 53
 REGISTERS
ACC 14
Check for Fetch
interrupts instruction
MBR ADD 72
from memory
MAR 2

Execute CIR ADD 72

Update
instruction Program PC 2
counter
MEMORY
Location Contents THE PROGRAM
The second
23 14 1 LDA 23
instruction is
53 26 copied into the 2 ADD 72
72 35 CIR 3 STA 53
 REGISTERS
ACC 14
Check for Fetch
interrupts instruction
MBR ADD 72
from memory
MAR 2

Execute CIR ADD 72

Update
instruction Program PC 3
counter
MEMORY
Location Contents THE PROGRAM
The program
23 14 counter is 1 LDA 23
updated to point
53 26 2 ADD 72
to the next
72 35 instruction 3 STA 53
 REGISTERS
ACC 14
Check for Fetch
interrupts instruction
MBR ADD 72
from memory
MAR 72

Execute CIR ADD 72

Update
instruction Program PC 3
counter
MEMORY
Location Contents THE PROGRAM
The address part
23 14 of the current 1 LDA 23
instruction is
53 26 2 ADD 72
placed in the
72 35 MAR 3 STA 53
 REGISTERS
ACC 14
Check for Fetch
interrupts instruction
MBR 35
from memory
MAR 72

Execute CIR ADD 72

Update
instruction Program PC 3
counter
MEMORY
The contents of THE PROGRAM
Location Contents the location
whose address 1 LDA 23
23 14
is in the MAR are
53 26 2 ADD 72
loaded into the
72 35 MBR 3 STA 53
 REGISTERS
ACC 49
Check for Fetch
interrupts instruction
MBR 35
from memory
MAR 72

Execute CIR ADD 72

Update
instruction Program PC 3
counter
MEMORY
Location Contents THE PROGRAM
The contents of
23 14 1 LDA 23
the MBR are
53 26 added to the 2 ADD 72
72 35 ACC 3 STA 53
 REGISTERS
ACC 49
Check for Fetch
interrupts instruction
MBR 35
from memory
MAR 72

Execute CIR ADD 72

Update
instruction Program PC 3
counter
MEMORY
Location Contents THE PROGRAM
The Status 1 LDA 23
23 14
Register is
53 26 checked for 2 ADD 72
72 35 interrupts 3 STA 53
 REGISTERS
ACC 49
Check for Fetch
interrupts instruction
MBR 35
from memory
MAR 3

Execute CIR ADD 72

Update
instruction Program PC 3
counter
MEMORY
Location Contents THE PROGRAM
The address of
23 14 the third 1 LDA 23
instruction is
53 26 2 ADD 72
copied from the
72 35 PC to the MAR 3 STA 53
 REGISTERS
ACC 49
Check for Fetch
interrupts instruction
MBR STA 53
from memory
MAR 3

Execute CIR ADD 72

Update
instruction Program PC 3
counter
MEMORY
Location Contents THE PROGRAM
The third
23 14 1 LDA 23
instruction is
53 26 read into the 2 ADD 72
72 35 MBR 3 STA 53
 REGISTERS
ACC 49
Check for Fetch
interrupts instruction
MBR STA 53
from memory
MAR 3

Execute CIR STA 53

Update
instruction Program PC 3
counter
MEMORY
Location Contents THE PROGRAM
The third
23 14 1 LDA 23
instruction is
53 26 copied into the 2 ADD 72
72 35 CIR 3 STA 53
 REGISTERS
ACC 49
Check for Fetch
interrupts instruction
MBR STA 53
from memory
MAR 3

Execute CIR STA 53

Update
instruction Program PC 4
counter
MEMORY
Location Contents THE PROGRAM
The program
23 14 counter is 1 LDA 23
updated to point
53 26 2 ADD 72
to the next
72 35 instruction 3 STA 53
 REGISTERS
ACC 49
Check for Fetch
interrupts instruction
MBR STA 53
from memory
MAR 53

Execute CIR STA 53

Update
instruction Program PC 4
counter
MEMORY
Location Contents THE PROGRAM
The address part
23 14 of the current 1 LDA 23
instruction is
53 26 2 ADD 72
placed in the
72 35 MAR 3 STA 53
 REGISTERS
ACC 49
Check for Fetch
interrupts instruction
MBR 49
from memory
MAR 53

Execute CIR STA 53

Update
instruction Program PC 4
counter
MEMORY
Location Contents THE PROGRAM
The contents of
23 14 1 LDA 23
the ACC are
53 26 copied into the 2 ADD 72
72 35 MBR 3 STA 53
 REGISTERS
ACC 49
Check for Fetch
interrupts instruction
MBR 49
from memory
MAR 53

Execute CIR STA 53

Update
instruction Program PC 4
counter
MEMORY
The contents of THE PROGRAM
Location Contents the MBR are
23 14 copied into the 1 LDA 23
memory location 2 ADD 72
53 49
whose address
72 35 3 STA 53
is in the MAR
 REGISTERS
ACC 49
Check for Fetch
interrupts instruction
MBR 49
from memory
MAR 53

Execute CIR STA 53

Update
instruction Program PC 4
counter
MEMORY
Location Contents THE PROGRAM
The Status 1 LDA 23
23 14
Register is
53 49 checked for 2 ADD 72
72 35 interrupts 3 STA 53
Done