UNIT-V

FPGA Design
 FPGA Design flow
Design specification

Programming FPGA by
Behavioural description downloading the bit stream

RTL Description(HDL)
Bit stream

Functional verification
Placement & Routing
and testing

Logic synthesis and Technology netlist

technology mapping
 FPGA Architecture

• CLB
• I/O Pads
• Interconnects
• Switch block
Configurable Logic Block (CLB)
 FPGA Technologies
• SRAM technology.
• Anti fuse technology.
• EPROM/EEPROM technology.
SRAM programming Technology
SRAM Cell
• It most widely used FPGA programming technology.
It holds their data in FPGA memory.
• The output of the memory cell is directly connected
to another circuit and state of the memory cell
continuously controls the circuit being configured.
• Each combinational logic element requires many
programming bits and each programming
interconnection point requires its own bit.
 Advantages
• SRAM based FPGA can be easily programmed
• SRAM based FPGA can be reprogrammed
during the system operation, providing
dynamically reconfigurable systems.
• The circuits used in the SRAM based FPGA can
be fabricated with standard VLSI process.
 Disadvantages
• SRAM configuration memory burns a
noticeable amount of power, even when the
program is not changed.
• The bits in the SRAM are susceptible to theft.
• SRAM based FPGAs have to be configured
every time after power goes up and down.
 Anti fuse technology
• Anti fuse is a one-time programmable.
• Fuses are permanently put in place.
• The anti-part of anti fuse comes from its
programming method.
• Instead of breaking a metal connection by
passing through a current through it, a link is
grown to make a connection.
• Programming is very slow because each anti
fuse must be programmed separately.
• Programming element is an anti fuse (high
impedance(open circuit) on low voltage and
low impedance (connection) on high voltage.
• Small area
• Non-volatile
• Irreversible( design errors can not be
corrected)
 Advantages
• Antifuse technology is nonvolatile.Design
remain as it is even the power is down.
• Delays due to routing are very small.
• Anti fuse FPGAs tend to require lower power.
• Theft problem is not there in anti fuse
technology.
 Disadvantages
• Anti fuse technology requires a complex
fabrication process.
• External programmer is required to program
or configure the design, after which the design
can not be changed.
 EPROM/EEPROM technology
• Switch is disabled by injecting charge on the
gate using high voltage between gate and
drain.
• The charge is removed by UV light.
Reprogramming through exposure to UV light.
• Non volatile.
• Slower programming than SRAM.
 Advantages
• No external permanent memory is needed to
program it at power up.

Disadvantages
• Extra processing steps
• Static power loss due to pull up resistor high
resistance.
 FPGA Families
• FPGA families are
– Altera flex
– Spartan
– Virtex
FPGA Families
Altera flex
• Basic Architecture of ALTERA FLEX 8000
– Grid of Logic Array Block(LABs) each consisting of 8 independently
programmable Logic Elements(LEs)
– LABs are connected in rows & columns ,connected by FastTrack
Interconnect with Input-Output elements(IOEs) at the edges
– Ends of interconnect connected to each having
• bidirectional I/O buffer
• Flip-flop to register input or output
– Logic Element has
• 4 I/P LUT
• Programmable Register -has 4 low skew global clock ,clear or preset control
signals from Dedicated input ,I/O pin or Internal signal from LAB local
interconnect
• Dedicated Carry & cascade chains
– 4 signals common to each LE in a LAB
• 2 used as clocks
• 2 used for clear/preset control
 XILINX XC4000
• Basic Architecture of
XC4000 consists of
• CLBs
• Local & Global routing
resources
• Programmable I/O buffers
• SRAM based memory
configuration
XC4000 CLB
• Each CLB consists of
– LUT
– Multiplexers
– Registers
– Path for control signal
• Each CLB contains 3 function generators (F,G,H)
– Each function generator is based on an LUT with 5ns delay
independent of function being implemented
– 2 Function generators(F & G) can generate any arbitrary function of 4
I/ps and third (H) can generate any Boolean functions of 3 I/Ps
– H function block can get inputs from either F & G LUTs or from
external inputs.
– The 3 Function generators are programmed to generate
• 2 different functions of 3 independent sets of variables-one function must be
registered with CLB
• An arbitary function of 5 variables
• An arbitary function of 4 variables together with some functions of 6 variables
• Some function of 9 variables
• Each CLB has 2 storage devices that can be configured as Edge
trigerred flipflops with common clock
– Storage elements get their inputs from function generators or from D
input
– The other elements can get an external input from H1 input
– Storage elements are driven by a global SR during power-up
• Function generators can also drive 2 outputs directly(X &
Y)and independently of the outputs of the storage elements

DEDICATED FAST CARRY & BORROW LOGIC

• F & G function generators have separate dedicated logic for
fast carry & borrow generation with dedicated routing to link
the extra signal to the function in the adjacent CLB
• Prebuilt carry chain within CLB can be used to generate a pair
of 2-bit words in one CLB
• F generates a0+b0; G generates a1+b1
• Fast carry will forward the carry to next CLB above or below
• Fast carry & borrow increases efficiency performance of
adders, subtractors, accumulators,comparators & counters
Distributed RAM:
• 3 Function generators can be used as RAM either 16X2 dual
port RAM or 32X1 single port RAM
• Don’t have block RAM but a group of CLBs form an array of
memory
 XILINX SPARTAN II FPGAs
• contains several logic & memory resources that can support
15K-200K system gates & up to 57Kb block RAM storage
• Contains flexible Input/output (I/O) interfaces
• Manufactured in 0.25/0.18um CMOS technology with 6-layers
metal for interconection
• High performance & high system frequency of 200MHz
• Provides advanced Clock Control with 4 Dedicated Delay Lock
Loops( DLL)
• Supports unlimited reprogramability
SPARTAN II ARCHITECTURE
• Each of four quadrants
of CLBs is supported by
DLL
• Bounded by 406bit
block RAM
• Periphery of the chip is
lined with IOBs
• Each CLBs contains four
logic cells organised as a
pair of slices
• Each logic cell has
• 4 i/p LUT
• Logic for carry and
control
• D F/F
• Each LUT can be configured as a
16X1 RAM(distributed) and the pair
of LUTs in a logic cell configured as
16X2 bit RAM or 32X1 Bit RAM
• IOBs are individually programmable
to support reference,output voltage
and termination voltagesfor high
speed memory & bus standards
• Each IOB has 3 registers functioning
as D F/F or as level sensitive latches:
• One register (TFF) used to register
the signal that controls
(synchronously) programmable
output buffer
• Second register(OFF) is
programmed to register a signal
from internal logic ( alternatively, a
signal from internal logic can pass
directly to the output buffer)
• Third device to register signal
coming from I/O pad
• Common clock
drives each
register but has an
independent clock
enable
• Programmable
delay element on
the input path
used to eliminate
the pad-to pad
hold time
 XILINX VIRTEX FPGAS
• Leading edge of Xilinx Technology
• Addresses 4 key factors influencing the solution to complex system-level
and system-on-chip (SoC) designs:
– Level of Integration
– Amount of embedded memory
– Performance(timing)
– Subsystem interfaces

ARCHITECTURE :
• The programmable device is comprised of input/output blocks (IOBs) and
internal configurable logic blocks (CLBs).
– Programmable I/O blocks provide the interface between package pins and the
internal configurable logic.
– leading-edge I/O standards are supported by the programmable IOBs.
 includes four major elements organized in a
regular array
 Configurable Logic Blocks (CLBs) provide
functional elements for combinatorial and
synchronous logic, including basic storage
elements. BUFTs (3-state buffers) associated
with each CLB element drive dedicated
segmentable horizontal routing resources.
 Block SelectRAM memory modules provide
large 18 Kbit storage elements of dual-port
RAM.
 Multiplier blocks are 18-bit x 18-bit dedicated
multipliers.
 DCM (Digital Clock Manager) blocks provide
self-calibrating, fully digital solutions for clock
distribution delay compensation, clock
multiplication and division, coarse- and fine-
grained clock phase shifting.
• A new generation of programmable routing resources called Active
Interconnect Technology interconnects all of these elements.
• The general routing matrix (GRM) is an array of routing switches.
• Each programmable element is tied to a switch matrix, allowing multiple
connections to the general routing matrix
• All programmable elements, including the routing resources, are controlled by
values stored in static memory cells. These values are loaded in the memory
cells during configuration and can be reloaded to change the functions of the
programmable elements.

Virtex-II Features

• Input/Output Blocks (IOBs):

IOBs are programmable and can be categorized as follows:
 Input block with an optional single-data-rate or double-data-rate (DDR) register
 Output block with an optional single-data-rate or DDR register, and optional 3-
state buffer, to be driven directly or through a single or DDR register
 Bidirectional block (any combination of input and output configurations)
• IOB blocks include six storage
elements, as shown in figure
• Each storage element can be
configured either as an edge-
triggered D-type flip-flop or as
a level-sensitive latch
• On the input, output, and 3-
state path, one or two DDR
registers can be used.
• Double data rate is directly
accomplished by the two
registers on each path,
clocked by the rising edges (or
falling edges) from two
different clock nets.
• The two clock signals are
generated by the DCM and
must be 180 degrees out of
phase
• There are two input, output,
and 3-state data signals, each
being alternately clocked out.
• These registers are either edge-triggered D-type flip-flops or level-sensitive latches.
• IOBs support the following single-ended I/O standards:
• LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
• PCI-X compatible (133 MHz and 66 MHz) at 3.3V
• PCI compliant (66 MHz and 33 MHz) at 3.3V
• CardBus compliant (33 MHz) at 3.3V • GTL and GTLP
• The IOB elements also support the following differential signaling I/O standards:
• LVDS • BLVDS (Bus LVDS) • ULVDS • LDT • LVPECL
• Two adjacent pads are used for each differential pair. Two or four IOB blocks connect to one
switch matrix to access the routing resources.

CLBs
• CLB resources include four slices and two 3-state buffers.
• Each slice is equivalent and contains:
– Two function generators (F & G)
– Two storage elements
– Arithmetic logic gates
– Large multiplexers
– Wide function capability
– Fast carry look-ahead chain
– Horizontal cascade chain (OR gate)
• The function generators F & G are configurable as 4-input look-up tables (LUTs), as 16-bit shift
registers, or as 16-bit distributed SelectRAM memory.
• The two storage elements are either edge-triggered D-type flip-flops or level-sensitive latches.
• Each CLB has internal fast interconnect and connects to a switch matrix to access general routing
resources.

Block SelectRAM Memory

The block SelectRAM memory resources are 18 Kb of dual-port RAM, programmable from 16K x 1 bit
to 512 x 36 bits, in various depth and width configurations.
Giga scale Dilemma
 Short channel effects
Five different physical phenomena have to be
considered in short-channel devices:
• Drain induced barrier lowering and Punchthrough
• Surface scattering
• Velocity saturation
• Impact ionization
• Hot electrons
 Drain-induced barrier lowering (DIBL)
• The electrons (carriers) in the channel face a
potential barrier that blocks their flows.
• The potential barrier, in small-geometry
MOSFETs, is controlled by a two-dimensional
electric field vector (in other words by both
VGS and VDS).
• If the drain voltage is increased the potential
barrier in the channel decreases, leading to
Drain-Induced Barrier Lowering (DIBL)
 Drain-induced barrier lowering (DIBL) and
Punchthrough
• Under DIBL condiction electrons can flow between
the source and drain even if VGS < VT.
• The channel current that flows in this case is called
subthreshold current Punchthrough.
• The DIBL phenomenon can be accompanied by the
so-called punchthrough, that occurs when the
depletion region surrounding the drain extends to
the source.
• Punchthrough minimized with thinner oxide, larger
substrate doping (and longer channel!)
Surface scattering
Velocity Saturation
Impact ionization
Hot electrons
 High-k Dielectric
• High-κ dielectric refers to a material with a
high dielectric constant (κ, kappa), as compared to
silicon dioxide
• used in semiconductor manufacturing processes where
they are usually used to replace a silicon dioxide
gate dielectric or another dielectric layer of a device.
• As metal-oxide-semiconductor field-effect transistors
(MOSFETs) have decreased in size, the thickness of the
silicon dioxide gate dielectric has steadily decreased to
increase the gate capacitance (per unit area) and
thereby drive current (per device width), raising device
performance.
• As the thickness scales below 2 nm, leakage currents
due to tunneling increase drastically, leading to high
power consumption and reduced device reliability
• Replacing the silicon dioxide gate dielectric with a high-κ
material allows increased gate capacitance without the
associated leakage effects.
 FINFET TECHNOLOGY
Basics OF FINFET:

• Type of Multigate MOSFET

• Widely used over Planer MOSFET
• FIN is channel in between source & drain
• Can have two or four or more FIN in same structure
• Advantages over FET
 Area of performance
 Lower leakage power
 Low voltage operation
 Lower retention voltage for SRAM
 It is btter control over current
 ADVANTAGES
• Lower power Consumption
• Operates at low voltage
• Operating speed is high
• Static Leakage current s reduced upto 90%
• Compact
 DISADVANTAGES
• Fabrication cost is higher than CMOS circuit
• Controlling fin depth is difficult
 Applications of FINFET
• Used in microprocessor
• Used In microcontroller
• Used in smart Phone
• Used in compact chip