Unit_1_LDCA_CS

Noida Institute of Engineering and Technology, GR.
Noida
(An Autonomous Institute)
School of Computer Science & Engineering in Emerging Technologies
Introduction
Unit: 1
Logic Design & Computer

Dr. Sarabjeet Kaur
Architecture (BCSAI0302)
Assistant Professor
B Tech (AI)- 3rd Sem NIET, Greater Noida
1
12/09/2024
Faculty Information
Dr. Sarabjeet Kaur (Assistant Professor, ECE)
Biography
She has completed her Ph.D. degree in the field of

Antenna from Bhopal University. She has
received her M.Tech degree in Digital
Communication Engineering from Rajiv Gandhi
University from Bhopal in 2008 and B.Tech
degree in Telecommunication Engineering from
Pt. Ravi Shankar university .
Currently, She is working as an Assistant
Professor in the Department of Electronics &
Communication Engineering in NIET, Greater
Noida, India. He has more than 15 years of
teaching & research experience.
12/09/2024 Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1 2
Evaluation scheme
Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

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Subject Syllabus

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Subject Syllabus
Subject Syllabus

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Subject Syllabus
Subject Syllabus

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Branch wiseInformation
Subject
Faculty Applications
Syllabus
Computer Science:
Understanding of Logic Design and Computer Architecture is required

for:
• Understanding of Logic on computer
• Performance analysis of practical software
• Parallel Software and its execution
• High performance databases
• Modern Compilers and Code optimization
• High performance game programming
Other applications
• Bio-informatics, Data science using python, Web programming
For high performance computing, we require COA background.

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Course Objective
• Discuss the basic concepts ,Logics and structure of computers.

• Understand concepts of register transfer logic and arithmetic
operations.
• Explain different types of addressing modes and memory
organization.
• Understand the concepts of memory system and Learn the different
types of memories to store data.
• Explain the various types of interrupts and modes of data transfer.

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Course Outcomes
Course outcomes : After completion of this course students will be able to
CO 1 Understand the basic structure and operation of a digital K1, K2

computer system
CO 2 Analyze the design of arithmetic & logic unit and understand the K1, K4
fixed point and floating-point arithmetic operations.
CO 3 Implement control unit techniques and the concept of Pipelining K3
CO 4 Understand the hierarchical memory system, cache memories K2

and virtual memory.
CO 5 Understand different ways of communicating with I/O devices K2
and standard I/O interfaces.

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Program Outcomes
• Program Outcomes are narrow statements that describe what the students
are expected to know and would be able to do upon the graduation.
• These relate to the skills, knowledge, and behavior that students acquire
through the programmed.
1. Engineering knowledge
2. Problem analysis 9. Individual and team work
3. Design/development of solutions 10. Communication
4. Conduct investigations of complex 11. Project management and
problems finance
5. Modern tool usage 12. Life-long learning
6. The engineer and society
7. Environment and sustainability
8. Ethics

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CO-PO Mapping
COMPUTER ORGANIZATION AND ARCHITECTURE

(ACSE 0305)
PO PO PO
CO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 10 11 12
CO1 3 2 1 1 1 1 1 - 1 1 1 2
CO2 2 2 2 2 1 1 - 1 1 1 1 2
CO3 3 2 2 1 2 2 1 1 2 2 1 2
CO4 3 2 2 2 2 1 1 - 1 1 1 2
CO5 2 2 2 1 2 - 1 - 1 2 2 2
Average 2.6 2 1.8 1.4 1.6 1 0.8 0.4 1.2 1.4 1.2 2

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Program Educational Objectives
PEO1: Solve real-time complex problems and adapt to technological

changes with the ability of lifelong learning.
PEO2: Work as data scientists, entrepreneurs, and bureaucrats for
the goodwill of the society and pursue higher education.
PEO3: Exhibit professional ethics and moral values with good
leadership qualities and effective interpersonal skills.

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Result Analysis
Department Result Individual Result
Computer 100%
Organization
and Architecture
Renewable 98.57%
Energy
Resources
Universal 90.74%
Human Values
Introduction to 95.61%
Microprocessor

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End Semester Question Paper Template
Question Paper
Template -100 Marks

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Prerequisite and Recap
• Basic knowledge of Digital Logic Design

• ALU Unit
• Control Unit
• Memory unit

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Brief Introduction about Subject
The Logic Design and Computer Architecture is one of the most

important and comprehensive subject that includes many foundational
concepts and knowledge used in design of a computer system. This
subject provides in-depth knowledge of internal working, structuring,
and implementation of a computer system.
The COA important topics include all the fundamental concepts such
as computer system functional units, processor micro architecture,
program instructions, instruction formats, addressing modes,
instruction pipelining, memory organization, instruction cycle,
interrupts and other important related topics.
Video link: https://www.youtube.com/watch?v=q6oiRtKTpX4

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Unit Content
• Introduction
Basics of Logic Design
• Basic of number System
• Boolean algebra
• Half Adder and Full Adder
• Half Subtractor and Full Subtractor
• Multiplexer
• Encoder and Decoder

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Unit Objective
• To understand the basic concepts and structure of computers.

• Basics of Logic Design

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Introduction to Topic 1
Topic Objective Mapping with CO
To understand different number systems. CO1
To understand number system conversion. CO1

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Number Systems
In digital electronics, the number system is used for representing the

information.
The number system has different bases and the most common of them
are the decimal, binary, octal, and hexadecimal.
The base or radix of the number system is the total number of the digit
used in the number system.
Suppose if the number system representing the digit from 0 – 9 then
the base of the system is the 10.

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Number
Number
Faculty systems
Systems
Information
Types of Number Systems

Some of the important types of number system are:
• Decimal Number System
• Binary Number System
• Octal Number System
• Hexadecimal Number System

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Decimal number
Number
Faculty systems
Systems
Information
• The number system is having digit 0, 1, 2, 3, 4, 5, 6, 7, 8, 9;

• this number system is known as a decimal number system because
total ten digits are involved.
• The base of the decimal number system is 10.

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Binary number
Number
Faculty systems
Systems
Information
• The modern computers do not process decimal number; they work

with another number system known as a binary number system
which uses only two digits 0 and1.
• The base of binary number system is 2 because it has only two digit
0 and 1.
• The digital electronic equipments work on the binary number
system and hence the decimal number system is converted into
binary system.
• The table is shown below the decimal, binary, octal, and
hexadecimal numbers from 0 to 15 and their equivalent binary
number.

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Binary number
Number
Faculty systems
Systems
Information

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Octal
Number
Faculty numbers
Systems
Information
• The base of a number system is equal to the number of digits used,

i.e., for decimal number system the base is ten while for the binary
system the base is two. The octal system has the base of eight as it
uses eight digits 0, 1, 2, 3, 4, 5, 6, 7.
• All these digits from 0 to 7 have the same physical meaning as by
decimal symbols, the next digit in the octal number is represented by
10, 11, 12, which are equivalent to decimal digits 8, 9, 10
respectively.
• In this way, the octal number 20 will represent the decimal digit and
subsequently, 21, 22, 23.. Octal numbers will represent the decimal
number digit 17, 18, 19… etc. and so on.

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Hexadecimal
Number
Faculty numbers
Systems
Information
• These numbers are used extensively in microprocessor. The

hexadecimal number system has a base of 16, and hence it consists
of the following sixteen number of digits.
• 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F.
• The size of the hexadecimal is much shorter than the binary number
which makes them easy to write and remember.
• Let 0000 to 000F representing hexadecimal numbers from zero to
fifteen, then 0010, 0011, 0012, …etc. Will represent sixteen,
seventeen, eighteen… etc. till 001F which represent thirty open and
so on.

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Code conversion
Number
Faculty Systems
Information
Conversion among base:

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Binary toNumber
decimal
Faculty Systems
conversion:
Information
• Multiply each bit by 2^n,where n is “weight” of the bits

• The weight is the position of the bit starting form zero from right.
• Add the result
• Example:

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Octal
Number
Facultyto decimal
Systems
Information
• multiplying each digit by 8^n bits where n the weight of the digits.
• the weight is the position of the digit starting from 0 on the right
• add the result
• example:

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Hexadecimal
Number
Faculty to decimal
Systems
Information

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Hexadecimal to decimal
Faculty
Number Systems conversion
Information
• Multiplying each digit by 16^n bits where n the weight of the digits.
• The weight is the position of the digit starting from 0 on the right
• Add the result
• Example:

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Decimal to binary
Faculty conversion
Information
Number Systems
Example : convert (52)10 to binary.

Sol:
(52)10 = (110100)2

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Decimal to octal
Number
Faculty conversion
Systems
Information
Example : Convert (378.93)10 to octal Sol:
Ans: (378.93)10 = (572.7341)8

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Binary Faculty
toNumber
decimal conversion
Systems
Information
Example : Convert (10101)2 to decimal.
(10101)2 = (21)10
Example : Convert (11011.101)2 to decimal.
(11011.101)2 = (27.625)10

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Daily
Number
Faculty Quiz
Systems
Information
• What do you mean by radix of any number system?

• Convert (1101.11)2 into decimal.
• Convert (267.89)10 into binary.
• The value of (011010101.110)2 in octal and hexadecimal are:
a) (236.6)8 and (D5.B)16
b) (235.6)8 and (D5.C)16
c) (325.6)8 and (D5.C)16
• The value of base x for (412)x = (153)8 is:
a) 9
b) 5
c) 8
d) 4
• Convert (ACB.8D)16 into binary and then convert it into octal number
system.
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Daily
Number
Faculty Quiz
Systems
Information
• Determine the value of if (193)x =(623)8

• Convert (100000011110)2 into hexadecimal and octal number
system without converting it to decimal.
• The solution to the quadratic equation k 2 – 11k + 22 = 0 are k = 3
and k = 6. What are the base of number systems?
• Convert (238.99)10 into binary, hexadecimal and octal.

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Recap
• The number system has different bases and the most common
of them are the decimal, binary, octal, and hexadecimal.
• The base or radix of the number system is the total number of
the digit used in the number system.
• Some of the important types of number system are:
Decimal Number System
Binary Number System
Octal Number System
Hexadecimal Number System
Name of Topic Objective of Topic Mapping with CO

Digital logic Gates, Students will be able
Half Adder and Full to know the Digital CO 1
Adder, Half logic Gates with the
Subtractor and Full functioning of adders
Subtractor. and subtractor.

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Digital logic Gates

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Digital
Digitallogic
Faculty Gates
logic Gates
Information

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Digital
Digitallogic
Faculty Gates
logic Gates
Information
What are Universal Gates?

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Digital
Digitallogic Gates
logic Gates
What are Universal Gates?

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Digital
Digitallogic
Faculty Gates
logic Gates
Information

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Digital
Digitallogic
Faculty Gates
logic Gates
Information

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Digital
Digitallogic
Faculty Gates
logic Gates
Information

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Digital
Faculty logic Gates
Information

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Digital
Digitallogic
Faculty Gates
logic Gates
Information

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Digital
Digitallogic
Faculty Gates
logic Gates
Information

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Digital
Digitallogic Gates
logic Gates

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Digital
Digitallogic Gates
logic Gates

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Digital
Digitallogic Gates
logic Gates

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Digital
Digitallogic Gates
logic Gates

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Digital
Digitallogic Gates
logic Gates
Boolean laws Description
Annulment law •A . 0 = 0
•A + 1 = 1
Identity law •A . 1 = A
•A + 0 = A
Idempotent law •A . A = A
•A + A = A
Complement law •A . AC = 0
•A + AC = 1
Commutative Law •A . B = B . A
•A + B = B + A
Associative law •A . (B . C) = (A . B) . C
•A + (B + C) = (A + B) + C
Distributive law •A(B + C) = AB + AC

•A + (BC) = (A + B)(A + C)
Absorption law •A.(A + B) = A

•A + (A . B) = A
Involution law •(A’)’ = A
De Morgan’s law •(A + B)C = AC . BC

•(A . B)C = AC + BC
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Digital
Digitallogic Gates
logic Gates

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Digital
Digitallogic Gates
logic Gates

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Digital
Digitallogic Gates
logic Gates

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Digital
Digitallogic Gates
logic Gates

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Digital
Digitallogic Gates
logic Gates

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Digital
Digitallogic Gates
logic Gates

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Digital
Digitallogic Gates
logic Gates

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Digital
Digitallogic Gates
logic Gates

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Digital
Digitallogic Gates
logic Gates

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Digital
Digitallogic Gates
logic Gates

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Digital
Digitallogic
Digital logicGates
logic Gates
Gates

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Digital
Digitallogic Gates
logic Gates

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Digital
Digitallogic Gates
logic Gates

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Digital
Digitallogic Gates
logic Gates

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Digital
Digitallogic Gates
logic Gates

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Digital
Digitallogic Gates
logic Gates

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Digital logic
Digital logic circuits
Gates
Digital logic circuits can be classified into “combinational” and

“sequential”. A combinational logic circuit is one whose output
solely depends on its current inputs. sequential circuits, on the
other hand, are built using combinational circuits and memory
elements called “flip-flops”. These circuits generate output that
depends on the current and previous states.
Types of Logic Circuits: There are two types of Digital circuits

depending on their output and memory used:
(i) Combinational circuit

(ii) Sequential circuit

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Digital logic
Gates
A combinational circuit consists of logic gates whose outputs at any time

are determined from only the present combination of inputs and they have
no memory.
A sequential circuit consists of logic gates whose outputs at any time are
determined from both the present combination of inputs and previous
output. That means sequential circuits use memory elements to store the
value of previous output.

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Digital logic
Gates
1. Combinational Circuits: These circuits are developed using AND,

OR, NOT, NAND, and NOR logic gates. These logic gates are building
blocks of combinational circuits. A combinational circuit consists of input
variables and output variables. In combinational circuits, the output at any
time is a direct function of the applied external inputs .

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Digital logic
Gates
2. Sequential circuits: A sequential circuit is specified by a time
sequence of inputs, outputs, and internal states. The output of a sequential
circuit depends not only on the combination of present inputs but also on
the previous outputs. Unlike combinational circuits, sequential circuits
include memory elements with combinational circuits. Some examples are
counters and shift registers. Generally, there are two types of storage
elements used: Latches, and Flip-Flops

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Half
HalfAdder
Adder
• Half adder is a combinational arithmetic circuit that adds two

numbers and produces a sum bit(S) and carry bit (C) as the ouput. If
A and B are the input bits ,then sum bit(S) is the X-OR of A and B
and the carry bit (C) will be the AND of A and B.
• The block diagram of half adder is:
• Truth Table for half adder is:

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Half
HalfAdder
Adder
• Logic diagram of half adder:
Full
Full Adder
Adder
• Full adder is developed to overcome the drawbacks of Half Adder

circuit. It can add two one-bit numbers A and B, sum S and carry C.
• The full adder is a three input and two output combinational circuit
• Truth Table : Block Diagram:

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Full
FullAdder
Adder
Full
FullAdder
Adder
Circuit diagram of full adder
Sum = A XOR B XOR Cin

Carry = AB + BCin + Cin A
Half Subtractor
• Half subtractor is an arithmetic circuit that subtracts two binary numbers

from each other, for example, X – Y to find the resulting difference
between the two numbers.
• Half subtractor produces a difference (D) by using a borrow bit(B) from
the previous column.
• Block Diagram and Truth Table :

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Half
HalfSubtractor
Subtractor
Logic Diagram of Half Subtractor :

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Full
FullSubtractor
Subtractor
• A full subtractor is a combinational circuit that performs subtraction

of two bits, one is minuend and other is subtrahend, taking into
account borrow of the previous adjacent lower minuend bit. This
circuit has three inputs and two outputs. The three inputs A, B and
Bin, denote the minuend, subtrahend, and previous borrow,
respectively. The two outputs, D and Bout represent the difference
and output borrow.
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Full
FullSubtractor
Subtractor

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Full
FullSubtractor
Subtractor
Full Subtractor using two half subtractor:
D = (A XOR B) XOR Bin & Bout = Bin (A XOR B)’ + A’B
Multiplexer
1. Multiplexer (MUX)
• It is a combinational circuit that has maximum of 2n data inputs, ‘n’
selection lines and single output line.
• One of these data inputs will be connected to the output based on the
values of selection lines.
• Multiplexers are also known as “Data n selector, parallel to serial
convertor, many to one circuit, universal logic circuit”

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Multiplexer
Multiplexer
2. Demultiplexer :
Demultiplexer is a data distributor which takes a single input and gives several
outputs. In demultiplexer we have 1 input and 2n output lines where n is the
selection line.

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Multiplexer
MUXand Demultiplexer
-DEMUX

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4x1 Multiplexer
4x1 Multiplexer
• 4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 &
s0 and one output Y.
• The block diagram of 4x1 Multiplexer is shown in the following figure.

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4x1
4x1Multiplexer
Multiplexer
• One of these 4 inputs will be connected to the output based on the

combination of inputs present at these two selection lines.
• Truth table of 4x1 Multiplexer is shown below.

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4x1
4x1Multiplexer
Multiplexer
• From Truth table, we can directly write the Boolean function for output, Y
as
• This Boolean function can be implemented using Inverters, AND gates &
OR gate. The circuit diagram of 4x1 multiplexer is shown in the following
figure.

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De-Multiplexer
De-Multiplexer (De-MUX)
• It is a combinational circuit that performs the reverse operation of
Multiplexer.
• It has single input, ‘n’ selection lines and maximum of 2n outputs.
• The input will be connected to one of these outputs based on the
values of selection lines.
• They are also known as “Data distributor, serial to parallel convertor,
one to many circuit”

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1x4 De-Multiplexer
1x4 De-Multiplexer
• 1x4 De-Multiplexer has one input I, two selection lines, s 1 & s0 and four
outputs Y3, Y2, Y1 &Y0.
• The block diagram of 1x4 De-Multiplexer is shown in the following
figure.

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1x41x4De-Multiplexer
De-Multiplexer
• The single input ‘I’ will be connected to one of the four outputs, Y 3 to
Y0 based on the values of selection lines s1 & s0.
• The Truth table of 1x4 De-Multiplexer is shown below.

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De-Multiplexer
• From the above Truth table, we can directly write the Boolean
functions for each output as

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De-Multiplexer
• These Boolean functions are implemented using Inverters & 3-input

AND gates.
• The circuit diagram of 1x4 De-Multiplexer is shown in the following
figure.

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Multiplexer
MUX and Demultiplexer
-DEMUX
Difference between of Multiplexer and
Demultiplexer
Multiplexer
Demultiplexer
Demultiplexer receives digital information from
Multiplexer processes the digital information a single source and converts it into several
from various sources into a single source. sources
It is known as Data Selector It is known as Data Distributor
Multiplexer is a digital switch Demultiplexer is a digital circuit
It follows combinational logic type It also follows combinational logic type
It has n data input It has single data input
It has a single data output It has n data outputs
It works on many to one operational principle It works on one to many operational principle
In time division Multiplexing, multiplexer is used In time division Multiplexing, demultiplexer is

at the transmitter end used at the receiver end

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Decoder
• The Decoder is a combinational circuit that has ‘n’ input lines and
maximum of output lines.
• One of these outputs will be active High based on the combination of
inputs present, when the decoder is enabled.
• That means decoder detects a particular code.
• The outputs of the decoder are nothing but the min terms of ‘n’ input
variables lines, when it is enabled.

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2 to 4 Decoder
• Let 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2, Y1 &
Y0.
• The block diagram of 2 to 4 decoder is shown in the following figure.

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2 to
2 to44Decoder
Decoder
• One of these four outputs will be ‘1’ for each combination of inputs when
enable, E is ‘1’.
• The Truth table of 2 to 4 decoder is shown below-

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2 to
2 to44Decoder
Decoder
• From Truth table, the Boolean functions for each output is

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2 to
2 to44Decoder
Decoder
• The circuit diagram of 2 to 4 decoder is shown in the following figure

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Encoder
• An Encoder is a combinational circuit that performs the reverse

operation of Decoder.
• It has maximum of 2n input lines and ‘n’ output lines.
• It will produce a binary code equivalent to the input, which is active
High.
• Therefore, the encoder encodes 2n input lines with ‘n’ bits. It is optional
to represent the enable signal in encoders.
2N:N

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4 to 2 Encoder
• Let 4 to 2 Encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 &
A 0.
• The block diagram of 4 to 2 Encoder is shown in the following figure.

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4 to
4 to22Encoder
Encoder
• At any time, only one of these 4 inputs can be ‘1’ in order to get the
respective binary code at the output.
• The Truth table of 4 to 2 encoder is shown below

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4 to
4 to22Encoder
Encoder
• From Truth table, the Boolean functions for each output is

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4 to
4 to22Encoder
Encoder
• We can implement the above two Boolean functions by using two input
OR gates.
• The circuit diagram of 4 to 2 encoder is shown in the following figure

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Encoder-Decoder

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Encoder
Encoder
8 : 3 Encoder (Octal to Binary) –

The 8 to 3 Encoder or octal to Binary encoder consists of 8 inputs : Y7 to Y0 and 3
outputs : A2, A1 & A0. Each input line corresponds to each octal digit and three outputs
generate corresponding binary code.
The figure below shows the logic symbol of octal to binary encoder:

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Encoder
Encoder
Logical expression for A2, A1 and

A0 :
A2 = Y7 + Y6 + Y5 + Y4
A1 = Y7 + Y6 + Y3 + Y2
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A0 = Y7 + Y5 + Y3 + Y1 108
Encoder
Encoder
The above two Boolean functions A2, A1 and A0 can be implemented using
four input OR gates :

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Daily Quiz
• What do you understand by universal gates?

• Realize a Ex-or gate with the help of NAND gate.
• Realize a OR gate using NAND gates.
• How an Ex-or gate can work as an inverter?
• What is the major difference between half-adders and full-adders?
a) Full-adders are made up of two half-adders
b) Full adders can handle double-digit numbers
c) Full adders have a carry input capability
d) Half adders can handle only single-digit numbers

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Recap
• Boolean Algebra is used to analyze and simplify the digital (logic)

circuits.
• It uses only the binary numbers i.e. 0 and 1.
• It is also called as Binary Algebra or logical Algebra.
• Binary logic consists of binary variables and a set of logical
operations.
• Here variable having two and only two distinct possible values: 1
and 0.
• There are three basic logical operations: AND, OR, and NOT.

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Name of Topic Objective of Topic Mapping with CO

Basics of Sequential Students will be able
Logic Circuits to know about CO 1
sequential logic
circuits like flip-flops,
registers and counters

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INTRODUCTION
Sequential Logic Representation
The word “Sequential” means that things happen in a “sequence”, one
after another and in Sequential Logic circuits, the actual clock signal
determines when things will happen next.

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Introduction
• It consists of a combinational circuit to which memory elements

are connected to form a feedback path.
• The memory elements are devices capable of storing binary
information within them. The binary information stored in the
memory elements at any given time defines the state of the
sequential circuit.
• The sequential circuit receives binary information from external
inputs. These inputs, together with the present state of the memory
elements, determine the binary value at the output terminals.
• Flip-flops, Latches and Counters and which themselves can be made
by simply connecting together universal NAND Gates and/or NOR
Gates in a particular combinational way to produce the required
sequential circuit.

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Introduction
There are two main types of sequential circuits. Their

classification depends on the timing of their signals.
A synchronous sequential circuit is a system whose
behaviour can be defined from the knowledge of its signals
at discrete instants of time.
The behaviour of an asynchronous sequential circuit
depends upon the order in which its input signals change
and can be affected at any instant of time.
The memory elements commonly used in asynchronous
sequential circuits are time-delay devices.
The basic memory elements are latches and flip-flops.
Latches are level sensitive and flip-flops are edge sensitive.

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Latches
• A Latch is a special type of logical circuit.

• The latches have low and high two stable states.
• A latch has a feedback path, so information can be retained by the
device. Therefore latches can be memory devices, and can store one
bit of data for as long as the device is powered.
• The latches can be constructed from two NAND gates or two NOR
gates.
Types of Latches:
• SR Latch.
• D Latch.
• J-K Latch.
• T Latch.

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SR Latch using NOR Gate
SR Latch using NOR Gate:

• SR latch stands for set/reset latch.
S R Qn+1 Q̅ n+1 Operation
0 0 Qn Q̅ n No change
0 1 0 1 Reset
1 0 1 0 Set
1 1 X X Invalid
• The cross-coupled connection from the output of one gate to the

input of the other gate constitutes a feedback path.
• Each latch has two outputs, Q and Q', and two inputs, set and
reset.
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SR Latch
Operation:
• If S = 1 and R = 0, Q becomes 1. Let us explain how.
• NOR gate always gives output 0 when at least one of the inputs is 1.
• So when S is applied as 1 the output of gate G2 i.e. is 0 irrespective
of the condition of second input Q to the gate.
• Now is the input of gate G1 so both the inputs of G1 become 0 as R
is already 0. So, the output of G1 is now or 1.
• So whatever may be the previous condition of Q, it always becomes
Q = 1 and Q’ = 0 when S = 1 and R = 0. This is called the SET
condition of the latch.

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SR Latch
• If S = 0 and R = 1, Q becomes 0. Let us explain how.

• As we already said, a NOR gate always gives output 0 when at least
one of the inputs is 1.
• So when R is applied as 1, the output of gate G1 i.e. Q is 0
irrespective of the condition of the second input to the gate.
• So, whatever may be the previous condition of Q, it always becomes
0 this 0 is then fed back to the input of gate G2. As here S is already
0, both inputs of G2 are 0. Hence the output of G2 i.e. will be 1. So,
Q = 0 and Q’ = 1 when, S = 0 and R = 1. This is called the RESET
condition of the latch.

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SR Latch
• If S = 0 and also R = 0, Q remains the same as it was.

• First suppose Q is previously 1.
• Now the inputs of G2 are 0 and 1 as S=0 and Q=1. So output of G2 is
0.
• Now both inputs of G1 are 0 as R=0 and Q’ =0. So the output of G1 is
1.
• Now suppose Q is previously 0.
• Now both inputs of G2 are 0 as S = 0 and Q = 0. So the output of G2
is 1.
• Now the inputs of G1 are 0 and 1 as R=0 and Q= 1. So the output of
G1 is 0.
• So it is proved that Q remains the same as it is when S = 0 and also R
= 0 in SR latch of flip flop.

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SR Latch
• If S = 1 and also R = 1, the condition of Q is totally unpredictable. Let

us explain how.
• First suppose Q is previously 1.
• Now both inputs of G2 are 1 as S = 1 and Q = 1. So output of G2 is 0.
• Now the inputs of G1 are 1 and 0 as R = 1 and Q’ = 0. So the output
of G1 is 0. That means Q is changed.
• Now Q is 0. So inputs of G2 are 1 and 0 as S = 1 and Q = 0. So the
output of G2 is 0. That means is unchanged.
• Now the inputs of G1 are 1 and 0 as R = 1 and Q’ = 0. So the output of
G1 is 0. That means Q is unchanged.
• So, when both S and R are 1, it becomes unpredictable whether the
value of output Q will be changed or unchanged. This condition of SR
latch normally avoided. As the latch is SET when S = 1(HIGH), the
latch is called Active High SR Latch.
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SR Latch using NAND Gate:
• SR Latch using NAND Gate:
S R Qn+1 Q̅ n+1 Operation
0 0 X X Invalid
0 1 1 0 Set
1 0 0 1 Reset
1 1 Qn Q̅ n No change

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Formation of the truth table
Now that we have looked at the circuit diagram for the SR latch, we will
not look at how the truth table is formed by looking at the different
input1:values
Case WhenofSS=and R. R = 0 (SET)
1 and
The NAND gates provide an output of 1 whenever there is an 0 in the

input to the logic gate. In the case of S = 1 and R = 0, the logic gate
connected to the reset input receives a 1, so it will output a 0. That 0
will then propagate to the NAND gate connected to the set input,
providing an output of 0 as 1 NAND with 1 is 0.
So the Q values will be 1, and the value of Q-bar will be 0 showing that
we set the value of Dr.
12/09/2024 the output
Sarabjeet Kaur QLogic
as Design
1. & Computer Architecture Unit 1 123

12/09/2024 124

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Flip Flops
• A Flip Flop is a memory element that is capable of storing one bit

of information.
• It is also called as Bistable Multivibrator since it has two stable
states either 0 or 1.
• There are following 4 basic types of flip flops-

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SR Flip Flop
Construction of SR Flip Flop By Using NAND Latch-

This method of constructing SR Flip Flop uses-
• NAND latch
• Two NAND gates
Logic Circuit-
• The logic circuit for SR Flip Flop constructed using NAND latch is
as shown below:

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SR Flip Flop
CLK S R Qn+1 Q̅ n+1 Operati

on
1 0 0 Qn Q̅ n No
Change
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 X X Invalid

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SR Flip Flop
Drawbacks of SR Flip Flop:

• The one major disadvantage of the S-R flip flop is that in the
condition when the clock is triggered the inputs become high
which is an undesirable condition because it causes invalid
input ,the condition in which you can't predict the output.
• So, in short we can say that the outputs in S-R flip flop are
undefined in that condition.
• JK flip flop is a refined & improved version of SR Flip Flop that
has been introduced to solve the problem of indeterminate state
that occurs in SR flip flop when both the inputs are 1.
• Input J behaves like input S of SR flip flop which was meant to
set the flip flop.
• Input K behaves like input R of SR flip flop which was meant to
reset the flip flop.
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JK Flip Flop
Construction of JK Flip Flop By Using SR Flip Flop Constructed
From NAND Latch-
• This method of constructing JK Flip Flop uses-
• SR Flip Flop constructed from NAND latch
• Two other connections
Logic Circuit-
• The logic circuit for JK Flip Flop constructed using SR Flip Flop
constructed from NAND latch is as shown below:
CLK J K Qn+1 Q̅ n+1 Operation

0 X X Qn Q̅ n
No Change
1 0 0 Qn Q̅ n
No change
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 Q̅ n
Qn Toggle
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JK Flip Flop
J K CLK Q(t+1) Comments

0 0  Q(t) No change
0 1  0 Reset
1 0  1 Set
1 1  Q(t)' Toggle
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JK Flip Flop
Differences between J K Flip Flop and S R Flip Flop

• Both JK flip flop and SR flip flop are functionally same.
• The only difference between them is-
• In JK flip flop, indeterminate state does not occur.
• In JK flip flop, instead of indeterminate state, the present state toggles.
• In other words, the present state gets inverted when both the inputs are 1.
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1
JK Flip Flop
Drawbacks of JK Flip Flop (Race around condition)
• The main drawback of the JK flip flop is the race around condition.
• It happens when both the input is 1.
• In race around condition output toggles more than one time.
• If that happens it will be very hard to predict the state of the flip flop.
• Assume present state is 1 and we are applying J=1 and K=1. what will
happen the output toggles next state should be 0.
• But what happens in real scenario the output will not ended up getting 0 it
will continues to toggle 0101010101010 it will go like that.
12/09/2024 Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 135
1
JK Flip Flop
There are three methods to eliminate race around condition as
described below:
Increasing the delay of flip-flop
The propagation delay (delta t) should be made greater than the
duration of the clock pulse (T). But it is not a good solution as
increasing the delay will decrease the speed of the system.
Use of edge-triggered flip-flop
If the clock is High for a time interval less than the propagation
delay of the flip flop then racing around condition can be
eliminated. This is done by using the edge-triggered flip flop
rather than using the level-triggered flip-flop.
Use of master-slave JK flip-flop
If the flip flop is made to toggle over one clock period then racing
around condition can be eliminated. This is done by using Master-
Slave JK flip-flop.

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D Flip Flop
• The D stands for "data"; this flip-flop stores the value that is on the
data line.
• It can be thought of as a basic memory cell.
• A D flip-flop can be made from a set/reset flip-flop by tying the set
to the reset through an inverter.
• One of the salient features of a D-type flip-flop is its ability to
"latch" and store and remember data.
• This property is used in creating a delay in progress of the data in
the circuit used.
• There are several applications in which a D-type flip-flop is used,
such as in frequency dividers and data latches.

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D Flip Flop
Logic Circuit:
• The circuit diagram of D flip – flop is shown in below figure.

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D Flip-flop
Operation of the D Flip-Flop
Given Below is the Operation of D Flip-Flop
• Case 1 (D=1):In this condition the flip-flop remains in its current

state regardless of clock input, Also the Output Q will remain set.
• Case 2 (D=0):In this condition the flip flop will change when D
input is 0 the Output Q will remain Reset.
D S
Q D CLK Q(t+1) Comments
C
R
CL 1  1 Set
K Q'
0  0 Reset

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D Flip-flop
• D flip-flop: single input D (data)

• D=HIGH a SET state
• D=LOW a RESET state
• Q follows D at the clock edge.
• Convert S-R flip-flop into a D flip-flop: add an inverter.
D S D CLK Q(t+1) Comments

Q
C 1  1 Set
CLK
R 0  0 Reset
Q'

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T Flip Flop
• The T or "toggle" flip-flop changes its output on each clock edge, giving an
output which is half the frequency of the signal to the T input.
• It is useful for constructing binary counters, frequency dividers, and
general binary addition devices.
• It can be made from a J-K flip-flop by tying both of its inputs high.
Construction
• We can construct a T flip – flop by connecting AND gates as input to the
NOR gate SR latch.
• These AND gate inputs are fed back with the present state output Q and
its complement Q’ to each AND gate.
• A toggle input (T) is connected in common to both the AND gates as an
input.

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T Flip Flop
CLK T Qn+1 Q̅ n+1

Operation
0 X Qn Q̅ n
No Change
1 0 Qn Q̅ n
No Change
1 1 Q̅ n
Qn Toggle
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T Flip-flop
• T flip-flop: single-input version of the J-K

flip flop, formed by tying both inputs
together.
T
Q T
J
Pulse Q
transition
C
CLK detector K
CLK
Q'
Q'
T CLK Q(t+1) Comments

0  Q(t) No change
1  Q(t)' Toggle

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T Flip-flop
Operation of the T Flip-Flop
Given Below is the Operation of T Flip-Flop
• Case 1 (T=0):In this condition the flip-flop remains in its current

state regardless of clock input, Also the Output Q will remain
unchanged unit the value of T will not change.
• Case 2 (T=1):In this condition the flip flop will change when T
input is 1,At each rising or falling edge of the clock signal the
output Q will be in complementary state.

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Shift Registers
• Shift Registers are sequential logic circuits, capable of storage and transfer of
data.
• This sequential device loads the data present on its inputs and then moves or
“shifts” it to its output once every clock cycle, hence the name is Shift
Register.
• A shift register basically consists of several single bit “D-Type Data Latches”,
one for each data bit, either a logic “0” or a “1”, connected together in a serial
type chain arrangement so that the output from one data latch becomes the
input of the next latch and so on.

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Shift Registers
Types of Shift Registers
Generally, shift registers operate in one of four different modes with the basic
movement of data through a shift register being:
• Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit
at a time, with the stored data being available at the output in parallel form.
• Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT” of
the register, one bit at a time in either a left or right direction under clock
control.
• Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time under
clock control.
• Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously

into the register, and transferred together to their respective outputs by the
same clock pulse.
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Shift Registers
Serial in - Serial out Shift Registers

• The SISO shift register is one of the simplest of the four
configurations as it has only three connections, the serial input (SI)
which determines what enters the left hand flip-flop, the serial
output (SO) which is taken from the output of the right hand flip-
flop and the sequencing clock signal (Clk). The logic circuit diagram
below shows a generalized serial-in serial-out shift register.

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Shift Registers
Serial in - Serial out Shift Registers

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Shift Registers
Serial in – Parallel out Shift Register

• These types of shift registers are used for the conversion of data
from serial to parallel.
• A 4-bits serial in – Parallel out shift register is illustrated in the
Image below.
• Lets assume that all the flip-flops ( FFA to FFD ) have just been
RESET (CLEAR input) and that all the outputs QA to QD are at logic
level “0” ie, no Dr.parallel
12/09/2024 dataLogic
Sarabjeet Kaur output.
Design & Computer Architecture Unit 1
149
Shift Registers
The serial data 1011 pattern presented at the SI input. This data is
synchronized with the clock CLK.

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Shift Registers
• Parallel-In Serial-Out Shift Register (PISO)

• The shift register, which allows parallel input (data is given separately
to each flip flop and in a simultaneous manner) and produces a serial
output is known as a Parallel-In Serial-Out shift register.
• The logic circuit given below shows a parallel-in-serial-out shift
register.
• The circuit consists of four D flip-flops which are connected. The
clock input is directly connected to all the flip-flops but the input
data is connected individually to each flip-flop through a multiplexer
at the input of every flip-flop.
• The output of the previous flip-flop and parallel data input are
connected to the input of the MUX and the output of MUX is
connected to the next flip-flop.
• All these flip-flops are synchronous with each other since the same
clock signal is applied to each flip-flop.
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Shift Registers
Parallel in – Serial out Shift Register
• For this type of shift register, the data is supplied in parallel.
• As this type of shift register converts parallel data, such as an
8-bit data word into serial format, it can be used to multiplex
many different input lines into a single serial DATA stream
which can be sent directly to a computer or transmitted over
a communications line

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Shift Registers
• Parallel-In Parallel-Out Shift Register (PIPO)

• The shift register, which allows parallel input (data is given
separately to each flip flop and in a simultaneous manner)
and also produces a parallel output is known as Parallel-In
parallel-Out shift register. The logic circuit given below shows
a parallel-in-parallel-out shift register. The circuit consists of
four D flip-flops which are connected. The clear (CLR) signal
and clock signals are connected to all 4 flip-flops. In this type
of register, there are no interconnections between the
individual flip-flops since no serial shifting of the data is
required. Data is given as input separately for each flip flop
and in the same way, output is also collected individually from
each flip flop.

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Shift Registers
Parallel in – Parallel out shift register

• For parallel in – parallel out shift register, the output data
across the parallel outputs appear simultaneously as the
input data is fed in.

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Counters
A Counter is a device which stores (and sometimes

displays) the number of times a particular event or process
has occurred, often in relationship to a clock
signal. Counters are used in digital electronics for counting
purpose, they can count specific event happening in the
circuit. Counters are sequential circuit that count the number of
pulses. The main properties of a counter are timing , sequencing ,
and counting. Counter works in two modes
Up counter
Down counter

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Counters
Counter Classification
Counters are broadly divided into two categories
Asynchronous counter
Synchronous counter
1. Asynchronous Counter
In asynchronous counter we don’t use universal clock, only first flip

flop is driven by main clock and the clock input of rest of the
following flip flop is driven by output of previous flip flops. We can
understand it by following diagram-

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Counters

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Counters
It is evident from timing diagram that Q0 is changing as soon as the rising

edge of clock pulse is encountered, Q1 is changing when rising edge of Q0 is
encountered(because Q0 is like clock pulse for second flip flop) and so on. In
this way ripples are generated through Q0,Q1,Q2,Q3 hence it is also
called RIPPLE counter and serial counter. A ripple counter is a cascaded
arrangement of flip flops where the output of one flip flop drives the clock
input of the following flip flop.

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Asynchronous (Ripple) Counters
2. Asynchronous Counter
Unlike the asynchronous counter, synchronous counter has one

global clock which drives each flip flop so output changes in
parallel. The one advantage of synchronous counter over
asynchronous counter is, it can operate on higher frequency than
asynchronous counter as it does not have cumulative delay because
of same clock is given to each flip flop. It is also called as parallel
counter.

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Asynchronous (Parallel) Counters

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Asynchronous (Parallel) Counters
From circuit diagram we see that Q0 bit gives response to each falling
edge of clock while Q1 is dependent on Q0, Q2 is dependent on Q1 and
Q0 , Q3 is dependent on Q2.
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Weekly Assignment
1. What is a combinational circuit?
2. Discuss the design process of a combinational circuit
3. Describe the operation of an adder.
4. Describe the operation of a multiplexer.
5. Describe Counters.
Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1 162
12/09/2024
Weekly
WeeklyAssignment
Assignment
1-Describe in detail the working of a Set-Reset (S-R) latch implemented
with NAND gates.
2-Describe the working of a NOR gate S-R latch.
3-Explain the working of a gated S-R latch.
4-Describe the working of a gated D-latch.
5-Explain the working of the T flip-flop.
6-Explain in detail the working of J-K flip-flop.
7-How will you convert an S-R flip-flop into a J-K flip-flop?
8-How will you convert a T flip-flop into a D flip-flop?
9-Illustrate the conversion of a J-K flipflop into a D flip-flop
10-Illustrate the conversion of a J-K flip-flop into a T flip-flop.
11-How will you convert a D flip-flop into a J-K flip-flop?
12/09/2024
Weekly
WeeklyAssignment
Assignment
1-Describe in detail the working of a Set-Reset (S-R) latch

implemented with NAND gates.
2. Explain in detail the working of J-K flip-flop.
3. How will you convert an S-R flip-flop into a J-K flip-flop?
4. How will you convert a T flip-flop into a D flip-flop?
5. Illustrate the conversion of a J-K flipflop into a D flip-flop
6. Illustrate the conversion of a J-K flip-flop into a T flip-flop.
7. How will you convert a D flip-flop into a J-K flip-flop?
12/09/2024
Daily Quiz
• What do you understand by sequential circuit?

• Differentiate between combinational and sequential circuits.
• Draw & explain NAND SR latch.
• Draw & explain NOR SR latch.
• What is the use of enable signal in latch?
Daily Quiz
1.When both inputs of a J-K flip-flop cycle, the output will ___________
a) Be invalid
b) Change
c) Not change
d) Toggle
2. Which of the following is correct for a gated D-type flip-flop?

a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH
3. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic

gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
FACULTY VIDEO LINKS, YOUTUBE &
NPTEL VIDEO LINKS AND ONLINE
COURSES DETAILS
Youtube/other Video Links:

• https://nptel.ac.in/courses/117/106/117106086/
• https://www.youtube.com/watch?v=2ecMG_OciLo&ab_channel=nptelhrd
nptelhrd
• https://www.youtube.com/watch?v=2ecMG_OciLo&ab_channel=nptelhrd
nptelhrd
Recap
• Shift Registers are sequential logic circuits, capable of storage and

transfer of data.
• A shift register basically consists of several single bit “D-Type Data
Latches”, one for each data bit, either a logic “0” or a “1”, connected
together in a serial type chain arrangement so that the output from
one data latch becomes the input of the next latch and so on.
Types of Shift Registers
Generally, shift registers operate in one of four different modes with
the basic movement of data through a shift register being:
• Serial-in to Parallel-out (SIPO)
• Serial-in to Serial-out (SISO)
• Parallel-in to Serial-out (PISO)
• Parallel-in to Parallel-out (PIPO)

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Glossary Questions
1. Construct a bus system for four registers with help of multiplexers.
2. A digital computer has a common bus system for 16 registers of 32
bits each. The bus is constructed with multiplexers.
a) How many selection inputs are there in each multiplexer?
b) What size of multiplexers are needed?
c) How many multiplexers are there in the bus?
3. What is Multiplexer?

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Old Question Papers - Sessional
Sessional 1
Sessional 2
Sessional 3
12/09/2024
Glossary questions
Q. Find the suitable glossary word for below questions:
[64, Low, Present as well as past output, Memory, 4, D Flip Flop, asynchronous
circuit, Clock, State, High, 64, ]
1. By placing an inverter between both inputs of SR Flip-Flop it becomes______.

2. A Flip Flop is a ______element that stores a binary digit as low or high voltage.
3. State diagram is graphical representation of _________table.
4. How many flip flops will be complemented in a 10-bit binary ripple counter to reach
the next count after the following count: 0111101111.
5. When a JK master-state flip flop the master is clocked when the clock is_____and
slave is triggered when the clock is______.
6. Race Condition occurs in__________.
7. In sequential circuit the output states depends upon________.
8. The minimum number of flip flop required to construct a mod-64 ripple counter
are_______.
9. If a counter is connected using flip flop then the maximum number of states that the
counter can count are_____.
10. When the LOAD input of a buffer is active the input word is stored on the next
positive______edge.
Old Question Papers
2018-19
2019-20
12/09/2024
Expected Questions for University Exam
1-Describe in detail the working of a Set-Reset (S-R) latch implemented with NAND
gates.
2-Describe the working of NAND gate version of S-R latch with the help of a transition
table.
3-Describe the working of a NOR gate S-R latch.
4-Explain the working of a gated S-R latch.
5-Describe the working of a gated D-latch.
6-Explain the working of the T flip-flop.
7-Explain in detail the working of J-K flip-flop.
8-How will you convert an S-R flip-flop into a J-K flip-flop?
9-How will you convert a T flip-flop into a D flip-flop?
10-Illustrate the conversion of a J-K flipflop into a D flip-flop
11-Illustrate the conversion of a J-K flip-flop into a T flip-flop.
12-How will you convert a D flip-flop into a J-K flip-flop?
13-Explain the operation of a J-K master-slave flip-flop.
14-What is the advantage of a JK flip-flop over an SR flip-flop?
REFERENCE
• R.P. Jain, “Modern Digital Electronics,” Tata McGraw Hill, 4th

edition, 2009.
• A. Anand Kumar, “Fundamental of Digital Circuits,” PHI 4th
edition, 2018.
• W.H. Gothmann, “Digital Electronics- An Introduction to Theory
and Practice,” PHI, 2nd edition, 2006.
• D.V. Hall, “Digital Circuits and Systems,” Tata McGraw Hill, 1989.
• A. K. Singh, “Foundation of Digital Electronics & Logic Design,”
New Age Int. Publishers.
• Subrata Ghosal, “Digital Electronics,” Cengage publication, 2nd
edition, 2018
Class Test
Q. N. Question Statement Marks CO BKL
1
Explain Full Adder with help of truth table and logic 5 CO1
K1,K2
diagram.
2 Convert the 5 CO1
K1,K2
(a)Binary Number 11001011 to Decimal Number
(b)Binary Number 1101101 to Octal Number
3 What is a Multiplexer. Describe the operation of an 5 CO1
K1,K2
8:1 Multiplexer.
4 Define Encoder. Describe any encoder with proper 5 CO1
K1,K2
logic diagram.
5 Explain Full Subtractor with help of truth table and 5 CO1
K1,K2
logic diagram.
6 Define Decoder. Describe 2:4 Decoder with proper 5 CO1
K1,K2
logic diagram.

12/09/2024 175
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YOU

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Noida Institute of Engineering and Technology, GR.

Logic Design & Computer

Dr. Sarabjeet Kaur (Assistant Professor, ECE)

She has completed her Ph.D. degree in the field of

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

Understanding of Logic Design and Computer Architecture is required

• Bio-informatics, Data science using python, Web programming

For high performance computing, we require COA background.

• Discuss the basic concepts ,Logics and structure of computers.

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

Course outcomes : After completion of this course students will be able to

CO 1 Understand the basic structure and operation of a digital K1, K2

CO 4 Understand the hierarchical memory system, cache memories K2

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

COMPUTER ORGANIZATION AND ARCHITECTURE

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

PEO1: Solve real-time complex problems and adapt to technological

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

Department Result Individual Result

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

• Basic knowledge of Digital Logic Design

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

The Logic Design and Computer Architecture is one of the most

Video link: https://www.youtube.com/watch?v=q6oiRtKTpX4

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

• To understand the basic concepts and structure of computers.

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

Topic Objective Mapping with CO

To understand different number systems. CO1

To understand number system conversion. CO1

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

In digital electronics, the number system is used for representing the

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

Types of Number Systems

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

• The number system is having digit 0, 1, 2, 3, 4, 5, 6, 7, 8, 9;

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

• The modern computers do not process decimal number; they work

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

• The base of a number system is equal to the number of digits used,

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

• These numbers are used extensively in microprocessor. The

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

Conversion among base:

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

• Multiply each bit by 2^n,where n is “weight” of the bits

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

Example : convert (52)10 to binary.

Dr. Sarabjeet Kaur Logic Design & Computer Architecture Unit 1

Example : Convert (378.93)10 to octal Sol: