VLSI

Physical
Design
Training
Overview
Physical Design Flow

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Physical Verification
AGENDA

 LVS
 DRC
 NAC – Antenna Check
 Density
 Verification Checks
 Q/A

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What is LVS?

 LVS stands for Layout Versus Schematics.

 LVS checks to ensures that physical layout matches
functional gate-level schematic.
 There are two stages of LVS Flow:
 First stage: Layout device extraction and layout netlist creation
 Second stage: Compares the created layout netlist with
Schematic netlist
 Extracts primitive devices (capacitors, resistors, pmos,

nmos, diodes) from layout

 Device layers may exist anywhere in the hierarchy

 All devices are found and extracted

 Compares: Ports (S,G,D), device model name (n), device sizes

(w,l) and device connectivity. This is done from the lowest
hierarchy to the top block

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Short

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Open

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DRC

 DRC (Design Rule Checking) verifies layout dimensions.

 DRCs look for violations in spacing, width, and enclosure of
polygons according to a specific set of process rules

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 DR violations

• Min Area
0.5

0.5 Metal Area = 0.5 * 0.5 =0.25

• Double jog Both sides < min metal width

• Poly neck
Within specific range of A and B values
B
A

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 NAC – Antenna Check

 NAC is Node Area Check

 The NAC check is performed to guarantee electrostatic
discharge (ESD) protection during the fabrication process.
 A NAC rule is a design rule check that verifies a minimum ratio
between layers on a per node basis.

 What are we trying to prevent: During processing of the

wafers, static charge (esd) builds up and is attracted to the
poly and metal. When too much static charge builds up, the
esd will travel down the wire to the gate (that it is attached to)
and give it a shock (just like rubbing your feet on the carpet
and touching someone). If the shock is too big, the gate be
damaged & can even blow up.

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NAC?

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NAC basics

 NAC (Node Antenna Check)

 during manufacturing, charge builds up on metals and vias during polishing
(planarization) and etch.
 If not discharged, the charge can damage transistor gates
 transistor can be destroyed
 transistor is electrically degraded (more of a problem if not found during scan testing)
 Also called Antenna (term in Icc) or IP (In Process Charging)
 red book rules for NAC are IP_*
 runset is called ipall

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Process Charging
 During silicon manufacturing, back-end process charging
induced high voltage and cause gate oxide breakdown.
Resulting:
 Immediate failure - blows up transistors
 Gradual failure - Transistor degradation over time
 Source of process charging can be result from plasma etch,
ILD deposition, implant or other generation of static charge
 Plasma is hot , +ve charged gas. As it etches the via-cut, it
deposits a positive charge
 The Larger the area & periphery of the metal connected to
the gate, larger Q becomes. => antenna effect or Node Area
Checking (NAC)

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Damascene Process Flow

Si
1. Start after 2. ILD 3. ILD Trench 4. Metal 5. Metal
(W) contact deposition pattern deposition CMP

6. SiN, ILD 7. ILD via 8. ILD trench 9. Metal 10. Metal

deposition pattern pattern deposition CMP

Repeat as necessary for MT2 – MT6

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Ratios and checking by layer

 Rules are expressed as ratios

 Ratio of exposed metal area to gate area
 e.g. rule 20 means that metal area is 20x gate area
 Note that vias are calculated separately to p and n gate areas
and metals are the sum of n and p gate areas
 NAC analysis is layer by layer
 This is an essential concept – must be able to see this to
understand what is going on

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layer by layer – example 1

A B

 In this example, M1 segment B and M2 segment C could

potentially cause NAC violations
 M1 segment A cannot cause a violation – not connected
to gate during manufacturing

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layer by layer – example 2

C B

 In this example
 M1 segment A could cause a violation
 The sum of the areas of C and B could cause a violation –
both are connected to gate during manufacturing

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Where does the charge go ?

 Identifying where the charge goes is key to

understanding the different rules
 All charge needs to end up in substrate
 Charge can conduct through the gate (unprotected)
 Charge can conduct through diffusion (protected)

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layer by layer example 3

D B
E A

 In this example
 Metal 1 segment A and metal 2 segment B can cause NAC violations
 Metal 3 segment C cannot cause an (unprotected) violation as it is
connected to diffusion (must meet 10000 rule)
 Metal 1 segment E and metal2 segment D can never cause violations
because they don’t connect to the gate at the time they are manufactured

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adding a (gnac) diode

 Unlimited protection
 Adds capacitance to net and leakage
 gnac – gated nac

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Fixing NAC violations

1. Make sure gate has direct path to diffusion

2. Jump metal layer to reduce amount of metal
touching gate (sometimes called jogging)
 jumping layers in a congested area is hard
3. Add a diode
4. Increase gate area

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example of jumping

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Adding a diode

 Place the diode as close as possible to the violating

pin
 Connect diode pin to the violating port using layers
that are lower than the violating via and metal
layers

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layer by layer example 4

B
C A

TAP GNAC

 GNAC prevents NAC violation on metal2

segment B
 GNAC does not prevent NAC violation caused
by metal1 segment A

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NAC rules

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 NAC rules

Met2
Victime gate

Met1

Layer A area / Layer B area = Ratio

Ratio > Maximum  Nac Violation!

Need to be fixed.

Layer A area
Layer B area
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 NAC rules

Fixing by jumper to upper level

Met3

Layer A area
Layer B area
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 NAC rules

Fixing by jumper to lower level

Met1

Layer A area
Layer B area This will NOT fix the violation !!
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 NAC rules

Fixing by Gnac device

(Gnac = discharge assistance device) Met2
M2 area / Gate area = Ratio
Ratio > Maximum, but a Gnac is present!
So the flow will check the rule:
Met1 M2 area / Z Gnac < 10.000

VSS ESD

ESD

ESD
Gnac device

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 Density
 Density
 Metal Density
 Base Density
 Via density

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 Density rules

 Density rules
 In order to be correctly generated, ALL layers in the chip must have their density within a specified
range. This check is performed within a specified window size.
 Example:
 Min Met2 density is 20% in windows of 105u x 105u

 Max Met2 density is 70% in windows of 35u x 35u

 Refer to red book for other layers rules

< 20% !
> 70% !

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 MFILL
 Metal fill is process requirement required on layers
 Each track of layers must be filled with a spacing rule in the
same layer.

 Mfill requires fill of tracks in 2 scenarios:

Active fill: Required only at places with VCC/VSS layers
creating some gaps and spacings.
Floating fill: All the empty spaces on the metal tracks.

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METAL & VIA DUMMIFICATION

 The purpose of the Dummification flow is to add non-design

metal pieces (dummies) on each metal layer to help preserve
layer planarity.
 Dummification also assists with meeting local & global metal
density requirements.
 We check metal & via densities both locally and globally.
 For the local check, an area has been defined which is then
stepped throughout the database
 Density is checked for both minimum and maximum bounds.

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 What is Fill and why do we need it?
There are three types of Fill we use  Base, Via, Metal
1) Basefill concerns all “base” layers typically including poly/gcn/tcn/n-well/n-diff/p-diff/etc. These layers are usually contained within our
standard cells.
2) Viafill concerns all via layers.
3) Metalfill concerns all metal layers, excluding base metals.

Fill is needed for several manufacturing purposes:

4) Polishing  need to hit a specified global and local density target for each layer to ensure smooth polishing of the silicon after each
layer is deposited.
a) With functional signal routes we may not hit these density targets, so we need to add in “dummy” fill pieces of metal/via to
reach these targets.
5) Correct shape printing  Max-spacing on some layers means we have to have a printed line in that layer at some exact distance or
distance range to ensure our routes are printed properly.
6) Basefill cells are needed to connect the n-well in gaps where no functional cells are present, in addition to providing regular poly
spacing requirements and meeting most tcn/gcn/via0 density requirements.
 Basefill Concept 1. All calls are on a grid and have a fixed height, but variable width.
2. The rest of the design must be filled in with various physical-only basefill cells (blue).

== Purple cells
Functional Std
Cells
 Basefill Concept
1. Basefill flow adds in physcial only cells of various types and widths.
2. There should be no white-space after basefill is complete.

== Purple cells
Functional Std
Cells

== Blue cells
Physical only
Std cells
1) Default dummy basefill was used just to connect the nwells so that we could close on LVS quickly. Once we are cmp clean, we remove
dummy basefill and replace it with real basefill
2) Real basefill is performed outside of ICC using an ICV runset. This runset will intelligently choose between a variety of basefill cells
depending on desired density, drc, debug (DFD), and manufacturing (DFM) considerations.

BASEFILL CELL TYPES

1. Tap (*tap*)  Used to tie the p-substrate to ground and the n-well to vcc. Tap spacing requirements are set to ensure good
p/g supply to the substrate and n-well. This is also why basefill cells are needed to connect gaps in the n-well between
functional cells, to ensure all n-wells are tied through the tap.

2. Bonus arrays (*bar*)  Provide base layer arrary of dummy transistors, which are used a reconfigurable arrays during
metal-only steppings to execute functional ECOs without touching the base layers.

3. Decaps (*vdc*)  Provides added capacitance on the powergrid to filter out high-freq noise. This is supposed to reduce
dynamic power, but is mainly used to meet via0 density requirements.

4. Bonus Array Decaps (*bdc*)  Same as Bonus Arrays, but adds in decap opportunistically if no m1 signal routes are
present.

5. Spacers (*spc*)  Empty spacers that contain poly and n-well for continuity.

6. Bonudary Edge halo cells (various like *hlv*)  Various types of halo cells (project specific) that are placed around the
boundaries of different hierarchical blocks to prevent DRC issues when stitching blocks into their parent hierarchy. These
are usually put into the design early during the floorplanning stage.

7. EBB Edge Spacers (*hlv*)  Halo cells around vertical edges of EBBs to maintain poly continuity.

8. Dummy Decap (*ddc*)  Like vdc decap cells, but has 16 permutations of cell types based on 4 sizes of p-transistors and 4
sizes of n-transistors. Preferred where no m1 is present and more than 6 free slots. Main purpose is to balance density,
decap functioning is just and adding benefit. Basefill flow will intelligently and opportunistically insert ddc cells wherever
possible to increase diffusion density.
a) Note that in some area, around a big EBBs, we may actually have a max diffusion density problem, in which case we
want to avoid these types of cells to forcably reduce the diffusion density.

9. Dummy Diffusion (*ddf*)  Like spacer cells, but contains n and p diffusion. Also has 4 sizes for p, 4 sizes for n  to hit
specific den requirements, basefill flow uses one of 16 different combinations intelligently.

10. Fiducial (*fid*)  Has specific diffusion pattern that is visually recognizable on the silicon for debug purposes and die
alignment to the machines. Requirement for these cells to be placed every so often, local density targets for these must be
hit.

11. DropInCell  DIC comes in as EBB, used by fab for planarization of the die.

12. Antenna nac diode (*gnc*)  Used to provide a path to ground for antenna viols. See antenna training ppt for much more
detailed description on this.
 Via/Metalfill Concept
1. Partitions contain preferred direction routing tracks
a) E.g. m1/3/5/7 are vertical layers & m2/4/6/8 are horizontal layers
2. Logical nets are routed in various metal layers almost always in predefined min-
widths.
a) Non-default routing (NDR) is generally used for clock/spine/power nets.
Extra width reduces resistance on these high current nets.
3. Why Fill?
1. Layer specific density requirements may not be met by logical signal
routes in each check box
a) Densities are checked within shifting boxes.
2. Layer specific max-spacing DRCs may not be met by signal routes.
3. Use fill to hit density targets and DRC requirements

M3 fill example

M3 Signal
Route
Viol max-
M3 FILL
spacing Route
Mfill Example Continued

Fill example

Signal
Route
FILL Route
Fill in to
fix the
forbidden
spacing
Max-spacing is fixed,
viol but still have density
problem.
Mfill Example Continued

Fill example

M3 Signal
Route
M3 FILL
Route

Now density of this

metal layer is
sufficient!
 ACTIVE FILL
Active fill is fill that is touching/overlapping with a real signal route. Active fill is often needed to fix:
1. DRC viols which would otherwise be unfixable without “stretching” the signal route
2. Min-density violations, often via density (by placing a dummy via on an active signal route)

Our LV flows and DRC checks do not care if a fill shape is touching an active signal, all DRC cares about is that the drawn
shapes do not violate manufacturability requirements. However, active fill does effect our PV (performance verification)
static timing analysis since the fill shape physically adds real capacitance to the route it’s touching. This added cap has a
real effect on performance of the silicon, so we must model these effects upfront in our PV models.

Active Fill example

Forbidden gap between two M3 signal shapes.

However, not enough room to fit a fully
0.9um detached m3 fill shape between them. For 0.8um
example, if the two m3 shapes are only 0.9um
away, we simply need to extend one of them by
0.8um.

M3 Signal
Route
M3 FILL
Route
Q/A

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ICC Manual Editing
Overview

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Rule of Thumb

First select layout object

Then invoke ICC command

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the Right Mouse Button

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Be familiar with Manual Editing Bind Keys
Hot Key Type Function (ICC
2007-03)
-----------------------------------------------------------------
--
+ Menu View->Zoom->Zoom In
- Menu View->Zoom->Zoom
Out
B remove_last_ruler_point
C Menu Edit->Copy
D Menu Edit->Delete
E Menu Verification->Next
Error
F Menu View->Zoom->Zoom
Fit All
M Menu Edit->Move/Resize
Q Menu Select->Query
Selection
R Menu View->Refresh
S Menu Edit->Stretch Wire
Creating your own bind key ifShift+C
necessary … Menu Edit->Create->Via...
Shift+L Menu Edit->Split
Ctrl+Y Wire "Menu
gui_set_hotkey -menu "Edit->Stretch -hot_key "s"Edit->Redo
Ctrl+ZShape andMenu
gui_set_hotkey -menu "Create->Net Edit->Undo
Via..." -hot_key "a"
gui_set_hotkey -tcl_cmd {gui_remove_last_ruler_point -window [gui_get_current_window -types Layout -mru]} -hot_key "b"

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Overview Wire Editing

Other useful command “HighLig

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 Move/Resize (m) command

his is double function command:

MOVE RESIZE

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 “Split command

Select a metal wire to active the

“split” command

before splitafter split

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Stretch Wire command

Select up/down
“Jog layer”
Default is “Same”

Before

After

Mouse pointer in Stretch Mode

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 1. select wire
Create VIA (shift + C)

. Invoke “create via” command

and migrate “net info” into editing
pop up form
3. Click to drop “X”
pointer to the via
drop off location

4. Click OK

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 Net shape and via Migrate net info
into editing form

Set layer direction

for both
horizontal & vertical

Select start/end
drop off via if editing
Needed vias insertion

Set merge net

Be sure it’s a routing
Track snap option

Select path

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“Move Pin (terminal) on Edge” command

after

before

Mouse pointer in Stretch Mode

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