0% found this document useful (0 votes)

11 views

lecture_slides_week13

Uploaded by

samiya364

Available Formats

Download as PPTX, PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

11 views

lecture_slides_week13

Uploaded by

samiya364

Available Formats

Download as PPTX, PDF, TXT or read online on Scribd

You are on page 1/ 21

Digital System

Design CE 325 L1
SPRING 2024
Instructor : Dr. Syed Arsalan Jawed
Associate Professor of Practice
[email protected]
Room : W-301
Office Hours : Monday 0930-1030, Wednesday 1430-1530, Friday 0930-1030
Installing and Using Open Source Synthesis
Tool Yosys
• Download OSS_CAD***.EXE for Windows 11 from the following link

• https://yosyshq.net/yosys/download.html

• Place the .exe in an appropriate folder and launch.

• Enable Developer Mode in Windows for the installation.

• Open CMD as Admin. Go to the folder where .exe was placed. Go inside OSS_CAD folder.

• Execute the following batch files

• Environment <enter>
• Start
• This will open a new terminal

• Yosys is now installed.

For Documents and Reps
• https://yosyshq.readthedocs.io/projects/yosys/en/latest/getting_start
ed/example_synth.html#demo-design

• The original manual of Yosys in pdf

• https://yosyshq.net/yosys/files/yosys_manual.pdf
• Read 1.1 to know about history of Yosys and OpenSource tools.

• We will refer to this document as Yosys Manual Pdf in the slides.

Three parts of Synthesis
• Compliance with HDLs Standards
• Handling behavioral description

• Optimizations
• Coarse Levels : at adders/multipliers level
• Fine Levels : at single bit gates level

• Technology Mapping
• Converting the design into a netlist of cells available in the target architecture
• FPGA : CLBs, LUT cells, special function units
• ASIC : process specific cell lib provided by fab
Typical Synthesis Flow in Yosys – section 3.3 from
Yosys Manual Pdf
#1 read input file to internal representation
read_verilog design.v
#2 convert high-level behavioral parts ("processes") to d-type flip-flops and muxes 5
proc
#3 perform some simple optimizations
Opt
#4 convert high-level memory constructs to d-type flip-flops and multiplexers
Memory
#5 perform some simple optimizations
Opt
#6 convert design to (logical) gate-level netlists
Techmap
#7 perform some simple optimizations
Opt
#8 map internal register types to the ones from the cell library
dfflibmap -liberty cells.lib
#9 use ABC to map remaining logic to cells from the cell library
abc -liberty cells.lib
#10 cleanup
opt
#11 write results to output file
Implementation Overview
Design data is read in using one of the frontend
modules.

The high-level HDL frontends for Verilog and VHDL

code generate an abstract syntax tree (AST) that is
then passed to the AST frontend.

The AST Frontend then compiles the AST to Yosys’s

main internal data format, the RTL Intermediate
Language (RTLIL).

Finally the design in RTLIL representation is converted

back to text by one of the backends
RTIL, just need to take an overview
Self-Study
• Quickly go through Chapter 8
• See what are different types of optimizations doing.
Using examples folder from the OSS-CAD-Suite
Installation
• Go to examples folder and quickstart folder

• Launch:
• Yosys demo.sv <enter>
• This will open a new terminal and would read in the Verilog of demo.sv which
has a simple 6-bit counter

• Note that you have <yosys> shell now.

• Execute:

• Hierarchy –check –top demo <enter>

• This will set top module as demo
Getting used to using examples
• Execute
• proc <enter>
• This converts processes into netlist
• It will find different constructs in the code and would convert it into hardware
• Muxes
• DFF
• Memories
• Latches
• Read the messages given by proc carefully.
• Complicated logic is still part of processes.
Dot File and GraphViz
• Use the show command to convert the synthesized logic into a .dot graphical representation.
• Show demo
• This will write demo.dot

• Install GraphViz 64-bit Windows from the following link:

• https://graphviz.org/download/
• Select all options

• Using a command prompt, go to the folder demo.dot was generated, run the following
command to generate an graphical SVG file:
• Dot –Tsvg demo.dot > demo.svg

• Open the demo.svg file in Web browser. This will show complete graphical dataflow of your
logic.

• Analyze that in detail.

Moving to FIFO from the Examples
Folder
• Move to /examples/fifo folder

• Reset the design

• Design –reset

• Read Fifo (follow the complete example from repo link above)
• Read_Verilog fif.sv
• hierarchy -check -top fifo
• Proc

• Generate fifo.dot and convert to svg and open in web browser

• Observe the following in fifo.svg

The highlighted fifo_reader block contains two instances of the addr_gen module, fifo_reader and
fifo_writer. Notice how the type is shown as $paramod\\addr_gen\\MAX_DATA=s32'.... This is a
“parametric module”: an instance of the addr_gen module with the MAX_DATA parameter set to the
given value.

The other highlighted block is a $memrd cell. At this stage of synthesis we don’t yet know what type
of memory is going to be implemented, but we do know that rdata <= data[raddr]; could be
implemented as a read from memory.

Also see that en and clock of $memrd are 1’bx so its not getting implemented as a memory block.

Observe RTIL names are marked with $.

Optimization Commands
• We now flatten the design to allow optimization between the
modules, so far the module boundary has been preserved.

• flatten

• Observe the svg again and comment on the difference before flatten
command.

• Self-Study : Send me back the differences you find.

• Run the following now:
• Clean or opt_clean
• To remove the unused modules.
• Observe svg again.
• Submit what differences you observe now.
Further Optimizations
• Opt_expr
• Opt_clean
• Check
• Opt –nodffe –nosdff
• Fsm
• Opt
• opt -nodffe -nosdff performing a set of simple optimizations on the design. This command
also ensures that only a specific subset of FF types are included, in preparation for the next
command: fsm - extract and optimize finite state machines. Both opt and fsm are macro
commands which are explored in more detail in Optimization passes and FSM handling
respectively.
Up until now, the data path for rdata has remained the same since rdata
output after flatten;;. However the next call to opt does cause a change.
Specifically, the call to opt_dff without the -nodffe -nosdff options is able to fold
one of the $mux cells into the $adff to form an $adffe cell; highlighted below:

SS : The online example claims the above, carefully traverse through your SVG to observe if
that has actually happened.
Further Optimizations
• Wreduce
• wreduce - reduce the word size of operations if possible. If we
run this we get the following: