Lecture

Lecture 15
15
Memory
Memory Test
Test
 Memory market and memory
complexity
 Notation
 Faults and failures
 MATS+ March Test
 Memory fault models
 March test algorithms
 Inductive fault analysis
 Summary

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 Density
Density and
and Defect
Defect
Trends
Trends
 1970 -- DRAM Invention (Intel) 1024 bits
 1993 -- 1st 256 MBit DRAM papers
 1997 -- 1st 256 MBit DRAM samples
 1 ¢ /bit --> 120 X 10-6
¢ /bit
 Kilburn -- Ferranti Atlas computer (Manchester
U.) -- Invented Virtual Memory
 1997 -- Cache DRAM -- SRAM cache + DRAM
now on 1 chip

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 Memory
Memory Cells
Cells Per
Per Chip
Chip

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 Test
Test Time
Time in
in Seconds
Seconds
(Memory
(Memory Size
Size n
n Bits
Bits))
Size Number of Test Algorithm Operations
n n n X log2n n3/2 n2

1 Mb 0.06
1.26 64.5 18.3 hr
4 Mb 0.25
5.54 515.4 293.2 hr
16 Mb 1.01
24.16 1.2 hr 4691.3 hr
64 Mb 4.03
104.7 9.2 hr 75060.0 hr
256 Mb 16.11
451.0 73.3 hr 1200959.9 hr
1 Gb 64.43
1932.8 586.4 hr 19215358.4 hr
2 Gb 128.9
3994.4 1658.6 hr 76861433.7 hr
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 Notation
Notation
 0 -- A cell is in logical state 0
 1 -- A cell is in logical state 1
 X -- A cell is in logical state X
 A -- A memory address
 ABF -- AND Bridging Fault
 AF -- Address Decoder Fault
 B -- Memory # bits in a word
 BF -- Bridging Fault
 C -- A Memory Cell
 CF -- Coupling Fault
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 Notation
Notation (Continued)
(Continued)
 CFdyn -- Dynamic Coupling Fault
 CFid -- Idempotent Coupling Fault
 CFin -- Inversion Coupling Fault
 coupling cell – cell whose change causes
another cell to change
 coupled cell – cell forced to change by a
coupling cell
 DRF -- RAM Data Retention Fault
 k -- Size of a neighborhood
 M -- memory cells, words, or address set
 n -- # of Memory bits
 N -- Number of address bits: n = 2N
 NPSF -- Neighborhood Pattern Sensitive Fault
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 Notation
Notation (Continued)
(Continued)

 OBF -- OR Bridging Fault

 SAF -- Stuck-at Fault
 SCF -- State Coupling Fault
 SOAF -- Stuck-Open Address
Decoder Fault
 TF -- Transition Fault

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 Faults
Faults
 System -- Mixed electronic,
electromechanical, chemical, and
photonic system (MEMS technology)
 Failure -- Incorrect or interrupted
system behavior
 Error -- Manifestation of fault in system
 Fault -- Physical difference between
good & bad system behavior

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 Fault
Fault Types
Types
 Fault types:
 Permanent -- System is broken and
stays broken the same way indefinitely
 Transient -- Fault temporarily affects
the system behavior, and then the
system reverts to the good machine --
time dependency, caused by
environmental condition
 Intermittent -- Sometimes causes a
failure, sometimes does not

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 Failure
Failure Mechanisms
Mechanisms

 Permanent faults:
 Missing/Added Electrical Connection
 Broken Component (IC mask defect or
silicon-to-metal connection)
 Burnt-out Chip Wire
 Corroded connection between chip &
package
 Chip logic error (Pentium division bug)

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 Failure
Failure Mechanisms
Mechanisms
(Continued)
(Continued)
 Transient Faults:
 Cosmic Ray
 An particle (ionized Helium atom)
 Air pollution (causes wire short/open)
 Humidity (temporary short)
 Temperature (temporary logic error)
 Pressure (temporary wire open/short)
 Vibration (temporary wire open)
 Power Supply Fluctuation (logic error)
 Electromagnetic Interference (coupling)
 Static Electrical Discharge (change state)
 Ground Loop (misinterpreted logic value)
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 Failure
Failure Mechanisms
Mechanisms
(Continued)
(Continued)
 Intermittent Faults:
 Loose Connections
 Aging Components (changed logic delays)
 Hazards and Races in critical timing paths
(bad design)
 Resistor, Capacitor, Inductor variances
(timing faults)
 Physical Irregularities (narrow wire -- high
resistance)
 Electrical Noise (memory state changes)

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 Physical
Physical Failure
Failure
Mechanisms
Mechanisms
 Corrosion
 Electromigration
 Bonding Deterioration -- Au package wires
interdiffuse with Al chip pads
 Ionic Contamination -- Na+ diffuses through
package and into FET gate oxide
 Alloying -- Al migrates from metal layers into
Si substrate
 Radiation and Cosmic Rays -- 8 MeV, collides
with Si lattice, generates n - p pairs, causes
soft memory error

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 Memory
Memory Test
Test Levels
Levels

Chip,
Array,
& Board

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 March
March Test
Test Notation
Notation
 r -- Read a memory location
 w -- Write a memory location
 r0 -- Read a 0 from a memory location
 r1 -- Read a 1 from a memory location
 w0 -- Write a 0 to a memory location
 w1 -- Write a 1 to a memory location
 -- Write a 1 to a cell containing 0
 -- Write a 0 to a cell containing 1
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 March
March Test
Test Notation
Notation
(Continued)
(Continued)

 -- Complement the cell contents

 -- Increasing memory addressing
 -- Decreasing memory addressing
 -- Either increasing or decreasing

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 More
More March
March Test
Test
Notation
Notation

A
-- Any write operation
 < ... > -- Denotes a particular fault, ...
 <I / F > -- I is the fault sensitizing condition,
F is the faulty cell value
 <I1, ..., In-1 ; In / F> -- Denotes a fault
covering n cells
 I1, ..., In-1 are fault sensitization
conditions in cells 1 through n - 1 for cell n
 In gives sensitization condition for cell n
 If In is empty, write In / F as F

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 MATS+
MATS+ March
March Test
Test
M0: { March element (w0) }
for cell := 0 to n - 1 (or any other order) do
write 0 to A [cell];
M1: { March element (r0, w1) }
for cell := 0 to n - 1 do
read A [cell]; { Expected value = 0}
write 1 to A [cell];
M2: {March element (r1, w0) }
for cell := n – 1 down to 0 do
read A [cell]; { Expected value = 1 }
write 0 to A [cell];

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 Fault
Fault Modeling
Modeling
 Behavioral (black-box) Model -- State
machine modeling all memory content
combinations -- Intractable
 Functional (gray-box) Model -- Used
 Logic Gate Model -- Not used
Inadequately models transistors &
capacitors
 Electrical Model -- Very expensive
 Geometrical Model -- Layout Model
 Used with Inductive Fault Analysis
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 Functional
Functional Model
Model

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 Simplified
Simplified Functional
Functional
Model
Model

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 Reduced
Reduced Functional
Functional
Model
Model (van
(van de
de Goor)
Goor)
 n Memory bits, B bits/word, n/B addresses
 Access happens when Address Latch contents
change
 Low-order address bits operate column
decoder, high-order operate row decoder
 read -- Precharge bit lines, then activate row
 write -- Keep driving bit lines during evaluation
 Refresh -- Read all bits in 1 row and
simultaneously refresh them

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 Subset
Subset Functional
Functional
Faults
Faults
Functional fault
a Cell stuck
b Driver stuck
c Read/write line stuck
d Chip-select line stuck
e Data line stuck
f Open circuit in data line
g Short circuit between data lines
h Crosstalk between data lines

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 Subset
Subset Functional
Functional
Faults
Faults (Continued)
(Continued)
Functional fault
i Address line stuck
j Open circuit in address line
k Shorts between address lines
l Open circuit in decoder
m Wrong address access
n Multiple simultaneous address access
o Cell can be set to 0 but not to 1 (or vice versa)
p Pattern sensitive cell interaction

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 Reduced
Reduced Functional
Functional
Faults
Faults

Fault
SAF Stuck-at fault
TF Transition fault
CF Coupling fault
NPSF Neighborhood Pattern Sensitive fault

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 Stuck-at
Stuck-at Faults
Faults
 Condition: For each cell, must read a 0 and a
A A
1.
 < /0> (< /1>)

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 Transition
Transition Faults
Faults
 Cell fails to make 0 1 or 1 0 transition
 Condition: Each cell must undergo a
transition and a transition, and be read
after such, before undergoing any further
transitions.
 < /0>, < /1>

< /0> transition fault

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 Coupling
Coupling Faults
Faults
 Coupling Fault (CF): Transition in bit j causes
unwanted change in bit i
 2-Coupling Fault: Involves 2 cells, special case
of k-Coupling Fault
 Must restrict k cells to make practical
 Inversion and Idempotent CFs -- special cases
of 2-Coupling Faults
 Bridging and State Coupling Faults involve any
# of cells, caused by logic level
 Dynamic Coupling Fault (CFdyn) -- Read or write
on j forces i to 0 or 1
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 Inversion
Inversion Coupling
Coupling
Faults
Faults (CFin)
(CFin)
 or in cell j inverts contents of cell i
 Condition: For all cells that are coupled,
each should be read after a series of
possible CFins may have occurred, and
the # of coupled cell transitions must be
odd (to prevent the CFins from masking
each other).
 < ; > and < ; >

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 Good
Good Machine
Machine State
State
Transition
Transition Diagram
Diagram

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 CFin
CFin State
State Transition
Transition
Diagram
Diagram

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 Idempotent
Idempotent Coupling
Coupling
Faults
Faults (CFid)
(CFid)
 or transition in j sets cell i to 0 or 1
 Condition: For all coupled faults, each should
be read after a series of possible CFids may
have happened, such that the sensitized CFids
do not mask each other.
 Asymmetric: coupled cell only does or
 Symmetric: coupled cell does both due to fault
 < ; 0>, < ; 1>, < ; 0>, < ; 1>

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 CFid
CFid Example
Example

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 Dynamic
Dynamic Coupling
Coupling
Faults
Faults (CFdyn)
(CFdyn)
 Read or write in cell of 1 word forces cell
in different word to 0 or 1
 <r0 | w0 ; 0>, <r0 | w0 ; 1>,
< r1 | w1 ; 0>, and <r1 | w1; 1>
 | Denotes “OR” of two operations
 More general than CFid, because a CFdyn
can be sensitized by any read or write
operation

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 Bridging
Bridging Faults
Faults
 Short circuit between 2+ cells or lines
 0 or 1 state of coupling cell, rather than coupling
cell transition, causes coupled cell change
 Bidirectional fault -- i affects j, j affects i
 AND Bridging Faults (ABF):
 < 0,0 / 0,0 >, <0,1 / 0,0 >, <1,0 / 0,0>, <1,1 / 1,1>
 OR Bridging Faults (OBF):
 < 0,0 / 0,0 >, <0,1 / 1,1 >, <1,0 / 1,1>, <1,1 / 1,1>

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 State
State Coupling
Coupling Faults
Faults
 Coupling cell / line j is in a given state y that
forces coupled cell / line i into state x
 < 0;0 >, < 0;1 >, < 1;0 >, < 1;1 >

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 Address
Address Decoder
Decoder Faults
Faults
(ADFs)
(ADFs)
 Address decoding error assumptions:
 Decoder does not become sequential
 Same behavior during both read & write
 Multiple ADFs must be tested for
 Decoders have CMOS stuck-open faults

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 Theorem
Theorem 9.2
9.2
 A March test satisfying conditions 1 & 2 detects
all address decoder faults.
 ... Means any # of read or write operations
 Before condition 1, must have wx element
 x can be 0 or 1, but must be consistent in test

Condition March element

1 (rx, …, w x )

2 (r x , …, wx)

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 Proof
Proof Illustration
Illustration

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 Necessity
Necessity Proof
Proof
 Removing rx from Condition 1 prevents A or
B fault detection when x read
 Removing rx from Condition 2 prevents A or
B fault detection when x read
 Removing rx or wx from Condition 1 misses
fault D2
 Removing rx or wx from condition 2 misses
fault D3
 Removing both writes misses faults C and
D1

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 Sufficiency
Sufficiency Proof
Proof
 Faults A and B: Detected by SAF test
 Fault C: Initialize memory to h (x or x).
Subsequent March element that reads h and
writes h detects Fault C.
 Marching writes h to Av. Detection: read Aw
 Marching writes h to Az. Detection: read Ay
 Fault D: Memory returns random result when
multiple cells read simultaneously. Generate
fault by writing Ax, Detection: read Aw or Ay
( or marches)
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Reduced
Reduced Functional
Functional Faults
Faults
Fault Functional fault
SAF a Cell stuck
SAF b Driver stuck
SAF c Read/write line stuck
SAF d Chip-select line stuck
SAF e Data line stuck
SAF f Open circuit in data line
CF g Short circuit between data lines
CF h Crosstalk between data lines
AF i Address line stuck
AF j Open circuit in address line
AF k Shorts between address lines
AF l Open circuit in decoder
AF m Wrong address access
AF n Multiple simultaneous address access
TF o Cell can be set to 0 (1) but not to 1 (0)
NPSF p Pattern sensitive cell interaction
Copyright 2001, Agraw VLSI Test: Lecture 15 42
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Fault
Fault Modeling
Modeling Example
Example 1
1

SA0
SAF
AF+SAF

SCF<0;0> SA0 SCF<1;1>

SA0 TF< /0>
TF< /1>

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Fault
Fault Modeling
Modeling Example
Example 2
2
SA1 gg SA1+SCF

ABF
ABF
SCF
SA0

ABF
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 Multiple
Multiple Fault
Fault Models
Models
 Coupling Faults: In real manufacturing, any #
can occur simultaneously
 Linkage: A fault influences behavior of another
 Example March test that fails:
 { (w0) ; (r0, w1); (w0, w1); (r1)}
 Works only when faults not linked

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 Fault
Fault Hierarchy
Hierarchy

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 Tests
Tests for
for Linked
Linked AFs
AFs
 Cases 1, 2, 3 & 5 -- Unlinked
 Cases 4 & 6 -- Linked

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DRAM/SRAM
DRAM/SRAM Fault
Fault Modeling
Modeling
DRAM or SRAM Faults Model
Shorts & opens in memory cell array SAF,SCF
Shorts & opens in address decoder AF
Access time failures in address decoder Functional
Coupling capacitances between cells CF
Bit line shorted to word line IDDQ
Transistor gate shorted to channel IDDQ
Transistor stuck-open fault SOF
Pattern sensitive fault PSF
Diode-connected transistor 2 cell short
Open transistor drain
Gate oxide short
Bridging fault
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SRAM
SRAM Only
Only Fault
Fault Modeling
Modeling

Faults found only in SRAM Model

Open-circuited pull-up device DRF
Excessive bit line coupling capacitance CF

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 DRAM
DRAM Only
Only Fault
Fault
Modeling
Modeling
Faults only in DRAM Model
Data retention fault (sleeping sickness) DRF
Refresh line stuck-at fault SAF
Bit-line voltage imbalance fault PSF
Coupling between word and bit line CF
Single-ended bit-line voltage shift PSF
Precharge and decoder clock overlap AF

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 Test
Test Influence
Influence on
on SRAM
SRAM
Fault
Fault Coverage
Coverage

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 Influence
Influence of
of Addressing
Addressing
Order
Order on
on Fault
Fault Coverage
Coverage

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 Critical
Critical Path
Path Length
Length
 Length of parallel wires separated by
dimension of spot defect size
 TFs and CFids happen only on long wires
Fault class Spot defect size (m)
<2 <3 <5 <7 <9 <2 <9
Stuck-at 78 213 227 269 269 51.3% 49.8%
Stuck-open 32 64 64 64 64 21.0% 11.9%
Transition 0 36 38 38 38 0% 7.0%
State Coup. 15 15 51 71 71 9.9% 13.2%
Idemp. Coup. 0 0 0 0 18 0% 3.3%
Data retention 27 29 80 80 80 17.8% 14.8%
Total 152 357 460 522 540 100% 100%

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 Fault
Fault Frequency
Frequency
 Obtained with Scanning Electron Microscope
 CFin and TF faults rarely occurred

Cluster # Devices Fault class

0 714 Stuck-at and Total failure
1 169 Stuck-open
2 18 Idempotent coupling
3 9 State coupling
4 8 ?
5 5 ?
7 26 Data retention
-- -- ?
14 2 ?
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 Functional
Functional RAM
RAM Testing
Testing
with
with March
March Tests
Tests
 March Tests can detect AFs -- NPSF
Tests Cannot
 Conditions for AF detection:
 Need ( r x, w x)
 Need ( r x, w x)
 In the following March tests, addressing
orders can be interchanged

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 Irredundant
Irredundant March
March Tests
Tests
Algorithm Description
MATS { (w0); (r0, w1); (r1) }
MATS+ { (w0); (r0, w1); (r1, w0) }
MATS++ { (w0); (r0, w1); (r1, w0, r0) }
MARCH X { (w0); (r0, w1); (r1, w0); (r0) }
MARCH { (w0); (r0, w1); (r1, w0);
C— (r0, w1); (r1, w0); (r0) }
MARCH A { (w0); (r0, w1, w0, w1); (r1, w0, w1);
(r1, w0, w1, w0); (r0, w1, w0) }
MARCH Y { (w0); (r0, w1, r1); (r1, w0, r0); (r0) }
MARCH B { (w0); (r0, w1, r1, w0, r0, w1);
(r1, w0, w1); (r1, w0, w1, w0);
(r0, w1, w0) }
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 Irredundant
Irredundant March
March Test
Test
Summary
Summary
Algorithm SAF AF TF CF CF CF SCF Linked
in id dyn Faults
MATS All Some
MATS+ All All
MATS++ All All All
MARCH X All All All All
MARCH C— All All All All All All All
MARCH A All All All All Some
MARCH Y All All All All Some
MARCH B All All All All Some

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 March
March Test
Test Complexity
Complexity

Algorithm Complexity
MATS 4n
MATS+ 5n
MATS++ 6n
MARCH X 6n
MARCH C— 10n
MARCH A 15n
MARCH Y 8n
MARCH B 17n

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 MATS+
MATS+ Example
Example
Cell
Cell (2,1)
(2,1) SA0
SA0 Fault
Fault

MATS+:
{ M0: (w0); M1: (r0, w1); M2: (r1, w0) }

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 MATS+
MATS+ Example
Example
Cell
Cell (2,
(2, 1)
1) SA1
SA1 Fault
Fault

MATS+:
{ M0: (w0); M1: (r0, w1); M2: (r1, w0) }

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 MATS+
MATS+ Example
Example
Multiple
Multiple AF
AF Type
Type C
C
 Cell (2,1) is not addressable
 Address (2,1) maps into (3,1) & vice versa
 Can’t write (2,1), read (2,1) gives random #

MATS+:
{ M0: (w0); M1: (r0, w1); M2: (r1), w0 }
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 RAM
RAM Tests
Tests for
for Layout-
Layout-
Related
Related Faults
Faults
Inductive Fault Analysis:
1 Generate defect sizes, location, layers
based on fabrication line model
2 Place defects on layout model
3 Extract defective cell schematic &
electrical parameters
4 Evaluate cell testing, using VLASIC
 Dekker found these faults:
 SAF, SOF, TF, SCF, CFid, DRF
 Proposed IFA-9 March test
 Delay means wait 100 ms
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 Inductive
Inductive Fault
Fault Analysis
Analysis
March
March Tests
Tests
Algor- Physical Defect Fault Coverage
ithm SAF TF AF SOF SCF CFid DRF Operations
IFA-9 All All All All All All 12n+Delays
IFA-13 All All All All All All All 16n+Delays

Algor-
ithm Description
IFA-9 { (w0); (r0, w1); (r1, w0); (r0, w1);
(r1, w0); Delay; (r0, w1); Delay; (r1) }
IFA-13 { (w0); (r0, w1, r1); (r1, w0, r0);
(r0, w1, r1), (r1, w0, r0),
Delay; (r0, w1); Delay; (r1) }
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 IFA
IFA Test
Test Validation
Validation
 Higher scores show better tests

Test Score Test Time

MATS+ 7 5n
MATS+ and Delay 18 8n + 2 Delay
March C 61 11n
March C and Delay 89 14n + 2 Delay
IFA-9 and Delay 91 12n + 2 Delay
IFA-13 80 13n
IFA-13 and Delay 92 16n + 2 Delay

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 Memory
Memory Testing
Testing
Summary
Summary
 Multiple fault models are essential
 Combination of tests is essential:
 March – SRAM and DRAM
 NPSF -- DRAM
 DC Parametric -- Both
 AC Parametric -- Both
 Inductive Fault Analysis is now required

Copyright 2001, Agraw VLSI Test: Lecture 15 65

al & Bushnell