ARM Processor Features

ARM Processor Features

 RISC: Reduced Instruction Set Computer
 ARM Processor Features
 Load/Store Architecture
ARM Processor Features
ARM Processor Features
 ‫‪ARM Processor Features‬‬

‫‪ ‬در پردازن ده ه ای‪ ARM‬اولي ه دس تورات ‪ 32‬بي تي بودن د‬

‫(دستورات ‪ )ARM‬که باعث مي شد طول برنامه بزرگ باشد‪.‬‬

‫‪ ‬در س ال ‪ 1995‬ميالدی ش رکت ‪ ARM‬پردازن ده ‪ ARM7TDMI‬را‬

‫معرفي نمود و دستورات تازه ای به اين پردازنده اضافه نمود‬
‫ک ه ‪ 16‬بي تي بودن د‪ .‬ب ه اين دس تورات دس تورات ‪ Thumb‬گفت ه‬
‫شد‪.‬‬

‫‪ ‬پردازن ده ‪ ARM7TDMI‬هم دس تورات ‪ Thumb‬و هم دس تورات‬

‫‪ ARM‬را پشتيباني مي نمايد‪.‬‬
 ‫‪ARM Processor Features‬‬
‫‪ ‬اگرچ ه اس تفاده از دس توران ن وع ‪ Thumb‬ب اعث مي ش ود ک ه‬
‫حجم کد برنامه کم شود ولی از آنجا که اين دستورات حالت‬
‫فش رده ای از دس تورات ‪ 32‬بي تي هس تند پردازن ده در قس مت‬
‫ديکدر دستورات سخت افزار خاصي براي تبديل اين دستورات‬
‫به حالت ‪ 32‬بيتي دارد و انجام اين تبديل زمانبر بوده و در نتيجه‬
‫کارايي پايين مي آيد‪.‬‬
ARM Processor Features
 ARM Processor Features
 Thumb is a 16-bit instruction set

 Optimized for code density from C code (~65% of ARM code size)

 Improved performance from narrow memory

 Subset of the functionality of the ARM instruction set

 Core has additional execution state – Thumb

 Switch between ARM and Thumb using BX instruction

 ‫‪ARM Processor Features‬‬
‫‪ ‬در پردازن ده ‪ Cortex-M0‬ک ه از س اختار ‪ ARMv6-M‬اس تفاده مي‬
‫نماي د دس تورات جدي دي ب ه اس م ‪ Thumb2‬اض افه ش ده اس ت ک ه‬
‫فقط با يک ديکدر مي توان هم دستورات ‪ 32‬بيتي و هم دستورات‬
‫‪ 16‬بيتي را ديکد نمود و در نتيجه عالوه بر کاهش حجم کد‪ ،‬کارايي‬
‫نيز باال مي رود‬
 ARM Processor Features
 The ARM7TDMI processor has two operating states:

 ARM state which executes 32-bit, word aligned ARM instructions

 THUMB state which can execute 16-bit, halfword aligned THUMB

instructions
ARM Processor Features
 ARM Processor Features
 ARM7 Processor Modes
 ARM Processor Features
 ARM7 Processor Modes
ARM Processor Features
ARM Processor Features
 ARM Processor Features
 Cortex-M Processor States and Modes

 The “state” and “mode” definitions of classic ARM processor is

different in the Cortex-M.

 Cortex-M processors always operate in Thumb state (ARM

instructions are not supported)

 There are only two modes in Cortex-M: Thread and Handler,

 ARM Processor Features
 Cortex-M Processor States and Modes
 ARM Processor Features
 Cortex-M Processor States and Modes
Processor mode and privilege levels for software execution:
The processor modes are:
Thread mode
Used to execute application software. The processor enters Thread mode when it
comes out of reset.
Handler mode
Used to handle exceptions. The processor returns to Thread mode when it has
finished all exception processing.
 ARM Processor Features
 Cortex-M Processor States and Modes
 ARM Processor Features
 Cortex-M Processor States and Modes

The privilege levels for software execution are:

Unprivileged
The software:
has limited access to the MSR and MRS instructions, and cannot use the CPS
instruction
cannot access the system timer, NVIC, or system control block
might have restricted access to memory or peripherals.
Privileged
The software can use all the instructions and has access to all resources.
ARM Processor Features
ARM Processor Features
ARM Processor Features
ARM Processor Features
ARM Processor Features
 ARM Processor Features
 Tightly Coupled Memory (TCM)

 TCM is fast SRAM located close to the core and guarantees the
clock cycles required to fetch instructions or data—critical for
real-time algorithms requiring deterministic behavior.

 TCMs appear as memory in the address map and can be

accessed as fast memory. An example of a processor with TCMs
is shown in Figure 2.14.
 ARM Processor Features
 DSP instructions

 Floating-point DSP  Fixed-point DSP uses

uses FPU SIMD DSP coprocessor
 Suitable for
 Suitable for
applications with applications with
known data range
wide data range
 Difficult to program
 Easy to program  Low hardware cost
 High hardware cost  Very energy efficient
 Not energy efficient
 ARM Processor Features
 DSP instructions: Parallel 8-bit Add and Subtract

SADD8 Rd, Rn, Rm SSUB8 Rd, Rn, Rm

UADD8 Rd, Rn, Rm USUB8 Rd, Rn, Rm
QADD8 Rd, Rn, Rm QSUB8 Rd, Rn, Rm
UQADD8 Rd, Rn, Rm UQSUB8 Rd, Rn, Rm
 ARM Processor Features
 Jazelle instructions
 The ARM designers introduced a third instruction set called Jazelle.

 Jazelle executes 8-bit instructions and is a hybrid mix of software

and hardware designed to speed up the execution of Java
bytecodes.
 ARM Processor Features
 Memory Management Unit (MMU)
 ARM Processor Features
 Memory Management Unit (MMU)
 ARM Processor Features
 Memory Protection Unit (MPU)

 The MPU is a programmable unit inside the processor that allows

privileged software to define memory access permissions and
memory attributes to different regions within the 4GB memory
space.

 All memory access is monitored by the MPU, which can trigger a

fault exception if unauthorized access is attempted.
 ARM Processor Features
 Memory Protection Unit (MPU)
 The MPU adds robustness to embedded systems in many different
ways.
 It can prevent stack overflows in one task from corrupting memory
belonging to another task.
 It can define regions of memory where access is never allowed by
instruction fetches, thus preventing any potential malicious code from
being executed from those regions.
 It can secure regions of RAM/SRAM from accidental corruption by defining
those regions as read-only.
 It can also define regions of memory as “shareable” when multiple masters
in the system have access to that region. By being shareable, the system is
required to ensure coherency for that region among its masters.
 ARM Processor Features
 Memory Protection Unit (MPU)
 ‫‪ARM Processor Features‬‬
‫‪ Trustzone Technology‬‬

‫‪ ‬امروزه اینترنت اشیاء به شکل روزافزونی در جهان‪ ،‬در حال‬

‫گسترش است‪.‬‬

‫‪ ‬در بسیاری از کاربردهای اینترنت اشیاء‪ ،‬اطالعات مهمی توسط‬

‫دس تگاه‌ها ذخ یره ی ا ردوب دل می‌ش ود‪ .‬بن ابراین نی از ب ه تض مین‬
‫امنیت این اطالعات نیز به وجود می‌آید‪.‬‬

‫‪ ‬این نی از به‌وس یله‌ی “معم اری ام نیت پلتف رم” ت أمین می‌ش ود‪.‬‬
‫یکی از فناوری‌های بسیار مؤثر در این زمینه‪ ،‬فناوری ‪Trustzone‬‬
 ‫‪ARM Processor Features‬‬
‫‪ Trustzone Technology‬‬
‫‪ ‬راهکار‪ TrustZone‬جداسازی سخت‌افزاری محیط امن از محیط‬
‫ناامن اس ت‪ .‬به‌طوری‌ک ه نرم‌افزاره ای ناامن امک ان دسترس ی‬
‫مستقیم به منابع محافظت‌شده را نداشته باشند‪.‬‬
‫‪ ‬نرم‌افزارها یا در محیط امن قرار دارند یا در محیط غیر امن‪،‬‬
‫امک ان س وییچ بین این دو به‌وس یله نرم‌اف زار دیگ ری ب ه ن ام‬
‫‪ secure monitor‬فراهم می‌شود‪.‬‬

‫‪ ‬درواق ع ایج اد مفه وم محی ط امن به‌وس یله مع رفی ی ک ح الت‬

‫جدی د پردازن ده‪ ARM‬ب ه ن ام “ح الت امن” ص ورت گ رفت‪ .‬این‬
‫حالت پردازنده که در مقابل حالت کار عادی آن قرار می‌گیرد‪.‬‬
 ‫‪ARM Processor Features‬‬
‫‪ Trustzone Technology‬‬

‫‪ ‬بدین طریق پلتفرم موردنظر به‌نوعی تبدیل به یک موجود دو‬

‫شخص یتی خواه د ش د‪ .‬هنگامی‌ک ه ح الت امن فع ال باش د‪،‬‬
‫نرم‌افزار در حال اجرا‪ ،‬نسبت به نرم‌افزاری که در حالت نرمال‬
‫ی ا ن اامن اج را می‌ش ود‪ ،‬نم ای متف اوتی از ک ل سیس تم دارد‪.‬‬
‫بن ابراین تواب ع سیس تمی‪ ،‬به‌خص وص تواب ع امنی تی و اطالع ات‬
‫رمزنگاری‌شده و حیاتی از محیط ناامن مخفی خواهند شد‪.‬‬
 ARM Processor Features
 Trustzone Technology
 ARM Processor Families

ARM7 ARM10

ARM9 ARM Families ARM11

Cortex family
 ARM processor family
Architecture Core bit-width Cores Profile
ARMv1 32 ARM1 Classic
ARMv2 32 ARM2, ARM250, ARM3 Classic
ARMv3 32 ARM6, ARM7 Classic
ARMv4 32 ARM8 Classic
ARMv4T 32 ARM7TDMI, ARM9TDMI, SecurCore SC100 Classic
ARMv5TE 32 ARM7EJ, ARM9E, ARM10E Classic
ARMv6 32 ARM11 Classic
ARMv6-M 32 ARM Cortex-M0, ARM Cortex-M0+, ARM Cortex-M1, SecurCore SC000 Microcontroller
ARMv7-A 32 ARM Cortex-A5, ARM Cortex-A7, ARM Cortex-A8, ARM Cortex-A9, ARM Cortex-A12, ARM Cortex-A15, ARM Cortex-A17 Application
ARMv7-M 32 ARM Cortex-M3, SecurCore SC300 Microcontroller
ARMv7-R 32 ARM Cortex-R4, ARM Cortex-R5, ARM Cortex-R7, ARM Cortex-R8 Real-time
ARMv7E-M 32 ARM Cortex-M4, ARM Cortex-M7 Microcontroller
ARMv8-A 32 ARM Cortex-A32 Application
ARMv8-A 64/32 ARM Cortex-A35, ARM Cortex-A53, ARM Cortex-A57, ARM Cortex-A72, ARM Cortex-A73 Application
ARMv8-A 64 ARM Cortex-A34 Application
ARMv8-M 32 ARM Cortex-M23, ARM Cortex-M33 Microcontroller
ARMv8-R 32 ARM Cortex-R52 Real-time
ARMv8-R 64 ARM Cortex-R82 Real-time
ARMv8.1-A 64/32 TBA Application
ARMv8.2-A 64/32 ARM Cortex-A55, ARM Cortex-A75, ARM Cortex-A76, ARM Cortex-A77, ARM Cortex-A78, ARM Cortex-X1, ARM Neoverse N1 Application
ARM Cortex-A65, ARM Neoverse E1 with simultaneous multithreading (SMT), ARM Cortex-A65AE (also having e.g. ARMv8.4 Dot
ARMv8.2-A 64 Application
Product; made for safety critical tasks such as advanced driver-assistance systems (ADAS))
ARMv8.3-A 64/32 TBA Application
ARMv8.3-A 64 TBA Application
ARMv8.4-A 64/32 TBA Application
ARMv8.4-A 64 ARM Neoverse V1 Application
ARMv8.5-A 64/32 TBA Application
ARMv8.5-A 64 TBA Application
ARMv8.6-A 64 TBA Application
ARMv8.7-A 64 TBA Application
ARMv9-A 64 ARM Cortex-A510, ARM Cortex-A710, ARM Cortex-A715, ARM Cortex-X2, ARM Cortex-X3, ARM Neoverse N2 Application
ARM Processor Families
Summary of Processors’ Characteristics
The Cortex-M processor family
 The Cortex-M processor family
 Cortex-M0
 A very small processor (starting from 12K gates) for low cost, ultra low
power microcontrollers and deeply embedded applications

 Cortex-M0+
 The most energy-efficient processor for small embedded system.
 Similar size and programmer’s model to the Cortex-M0 processor, but with
additional features like single cycle I/O interface and vector table relocations
 Cortex-M1
 A small processor design optimized for FPGA designs and provides Tightly
Coupled Memory (TCM) implementation using memory blocks on the
FPGAs. Same instruction set as the Cortex-M0
 The Cortex-M processor family
 Cortex-M3

 A small but powerful embedded processor for low-power microcontrollers

that has a rich instruction set to enable it to handle complex tasks quicker.

 It has a hardware divider and Multiply-Accumulate (MAC) instructions.

 In addition, it also has comprehensive debug and trace features to enable

software developers to develop their applications quicker
 The Cortex-M processor family
 Cortex-M4

 It provides all the features on the Cortex-M3, with additional instructions

target at Digital Signal Processing (DSP) tasks, such as Single Instruction
Multiple Data (SIMD) and faster single cycle MAC operations.

 In addition, it also have an optional single precision floating point unit that
support IEEE 754 floating point standard
 The Cortex-M processor family
 Cortex-M7

 High-performance processor for high-end microcontrollers and processing

intensive applications.

 It has all the ISA features available in Cortex-M4, with additional support
for double-precision floating point, as well as additional memory features
like cache and Tightly Coupled Memory (TCM)
 ARM Cortex-M optional components
Arm Core Cortex M0 Cortex M1 Cortex M3 Cortex M4 Cortex M7

SysTick 24- Optional Optional Yes Yes Yes

bit Timer (0,1) (0,1) (1) (1) (1)
Bit-Band memory No No Optional Optional Optional
Memory Protection Optional Optional Optional
Unit (MPU)
No No
(0,8) (0, 8) (0, 8, 16)
Optional
Instruction Cache No No No No
(up to 64KB)
Optional
Data Cache No No No No
(up to 64KB)
Instruction TCM Optional Optional
(ITCM) Memory
No No No
(up to 1MB) (up to 16MB)
Data TCM Optional Optional
(DTCM) Memory
No No No
(up to 1MB) (up to 16MB)
Vector Table Offset Optional Optional Optional Optional
Register (VTOR)
No
(0,1) (0,1) (0,1) (0,1)
 ARM Cortex-M instruction variations
Arm Core Cortex M0 Cortex M1 Cortex M3 Cortex M4 Cortex M7
ARM architecture ARMv6-M ARMv6-M ARMv7-M ARMv7E-M ARMv7E-M
Computer architecture Von Neumann Von Neumann Harvard Harvard Harvard
Instruction pipeline 3 stages 3 stages 3 stages 3 stages 6 stages
Interrupt latency 23 for NMI 12 cycles
16 cycles 12 cycles 12 cycles
(zero wait state memory) 26 for IRQ 14 worst case
Thumb-1 instructions Most Most Entire Entire Entire
Thumb-2 instructions Some Some Entire Entire Entire
Multiply instructions
Yes Yes Yes Yes Yes
32x32 = 32-bit result
Multiply instructions
No No Yes Yes Yes
32x32 = 64-bit result
Divide instructions
No No Yes Yes Yes
32/32 = 32-bit quotient
Saturated math instructions No No Some Yes Yes
DSP instructions No No No Yes Yes
Single-Precision (SP)
No No No Optional Optional
floating-point instructions
Double-Precision (DP)
No No No No Optional
floating-point instructions
 STM32 Part number decoding
 Example:
 STM32F407VG, split into STM32 F4 07 V G, means: F4
series, 07 subtype, 100 pin, 1024 KB flash
 Decoding:
 STM32 xx ww y z
 xx – Series family
 ww – Subtype, differs by each series family
 y – Package pin count
 z – Flash memory size
 Part number decoding: STM32 xx ww y z
Family: [xx]
Code Core Max freq [MHz] Max FLASH [KB] Max SRAM [KB] Target
F0 Cortex-M0 48 256 32 Mainstream
F1 Cortex-M3 72 1024 96 Mainstream
F2 Cortex-M3 120 1024 128 High performance
F3 Cortex-M4F 72 512 80 Mainstream
F4 Cortex-M4F 180 2048 384 High performance
F7 Cortex-M7F 216 2048 512 High performance
G0 Cortex-M0+ 64 512 144 Mainstream
G4 Cortex-M4F 170 512 128 Mainstream
H7 Cortex-M7F 480 2048 1024 High performance
L0 Cortex-M0+ 32 192 20 Ultra low power
L1 Cortex-M3 32 512 80 Ultra low power
L4 Cortex-M4F 80 1024 320 Ultra low power
L4+ Cortex-M4F 120 2048 640 Ultra low power
L5 Cortex-M33F 110 512 256 Ultra low power
U5 Cortex-M33F 160 2048 786 Ultra low power
WB Cortex-M4F 64 1024 256 Wireless
WL Cortex-M4 48 256 64 Wireless
 Part number Package pin count [y] FLASH memory size [z]
Code Number of pins Code FLASH size [KB]

decoding: A
B
169
208
4
6
16
32
C 48 8 64
STM32 xx ww y z F 20 B 128
G 28
Z 192
H 40
STM32 L4 76 V G I 176
C
D
256
384
J 8/72
E 512
K 32
F 768
M 81
G 1024
N 216
Cortex-M4F Q 132 H 1536
I 2048
LQFP100 package R 64
T 36
U 63
V 100
Z 144

1 Mbyte of Flash