ECE

Dr. Richa Srivastava

Associate Professor

Photo VII
VLSI Design
KEC 072
Introduction to VLSI
 Outline
Brief history
Moore’s Law
Classification of integration
VLSI Technology
 Introduction: A brief History
 First integrated circuit flip-flop with two transistors –built in 1958 by Jack Kilby at Texas
Instruments

 In 2008, Intel’s Itanium microprocessor contained more than 2 billion transistors

 Compound annual growth rate of 53% over 50 years

 No other technology in history has sustained such a high growth rate lasting for so long.
Introduction: A brief History
 During the first half of the twentieth century, electronic circuits used large,
expensive, power-hungry, and unreliable vacuum tubes

 In 1947, first functioning point contact transistor built by John Bardeen and Walter
Brattain, at Bell Laboratories

 The invention of the transistor earned the Nobel Prize in Physics in 1956
 Introduction: A brief History
 Ten years later, Jack Kilby at Texas Instruments realized the potential for miniaturization
if multiple transistors could be built on one piece of silicon.

 Kilby received the Nobel Prize in Physics in 2000 for the invention of the integrated
circuit.
Introduction: A brief History
 After invention of the point contact transistor, the bipolar junction transistor
developed by Bell Labs
 Advantage: More reliable, less noisy, and more power-efficient
 By the 1960s, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)
began to enter production
 Compelling advantage: they draw almost zero control current while idle
 Comes in two flavors: nMOS and pMOS, using n-type and p-type silicon,
respectively.
Introduction: A brief History
 In 1963, Frank Wanlass at Fairchild described the first logic gates using MOSFETs

 Fairchild’s gates used both nMOS and pMOS transistors, earning the name
Complementary Metal Oxide Semiconductor, or CMOS

 Circuits used discrete transistors but consumed only nanowatts of power, six orders
of magnitude less than their bipolar counterparts.
Introduction: A brief History
 In the 1970s Intel pioneered nMOS technology with its 1101 256-bit static random access
memory and 4004 4-bit microprocessor

 nMOS process -- less expensive than CMOS but nMOS logic gates still consumed power
while idle

 CMOS processes widely adopted replaced nMOS and bipolar processes for nearly all digital
logic applications
MOORE’S LAW
 Regarding this IC technology “Gordon Moore ” (co‐founders of Intel Corporation )
introduced a law

 For every 18 months transistors count are doubled

MOORE’S LAW

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E.
Weste and David Money Harris
 A corollary of Moore’s law
Dennard’s Scaling Law
 As transistors shrink, they become faster, consume less power, and are cheaper to
manufacture

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E.
Weste and David Money Harris
Classification of integration of chips
 SSI - <10 gates
 MSI - 100-1000
 LSI - 1000-20000
 VLSI - 1000000-100lakhs *
 Featur size dectreases integration increases
 WHAT IS VLSI ?
 VLSI: Very Large Scale Integration
 process of creating an integrated circuit (IC) by combining thousands of transistors
into a single Silicon Chip.

Feature size
 refers to the minimum dimension of a transistor that can be built reliably
 1971-feature size of 10 um
 2008-feature size of 45 nm
progression of process generations

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste and
David Money Harris
Key points
Moore’s Law has become a self-fulfilling prophecy
Semiconductor technology has moved from SSI to VLSI
Transistors cannot be smaller than atoms (scaling cannot
go on forever)
Outline
 MOS Transistor
CMOS inverter
CMOS Logic
Compound gates using CMOS Logic
MOS Transistor
 MOS Transistors
A Metal-Oxide-Semiconductor (MOS) structure--created by
superimposing several layers of conducting and insulating
materials to form a sandwich-like structure.

Manufactured using a series of chemical processing steps ---

oxidation of the silicon, selective introduction of dopants, and
deposition and etching of metal wires and contacts.
Types of MOS Transistor
 NMOS and PMOS
 Transistor operation--controlled by electric fields – that’s why Metal Oxide
Semiconductor Field Effect Transistors (MOSFETs)
 Cross-sections and symbols

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E.
Weste and David Money Harris
Outline
Structure of MOS Transistor
Different modes of operation
Characteristic curve
Structure of MOSFET

Source: CMOS Digital Integrated Circuit, Sung & Yusuf, 3rd

edition)
Symbol

Source: CMOS Digital Integrated Circuit, Sung & Yusuf, 3rd

edition)
Operation: Cutoff mode
VDS ≠ 0, VGS≤0 No Channel  ID=0
VT minimum gate voltage to form Sufficient Channel

Source: CMOS Digital Integrated Circuit, Sung & Yusuf, 3rd

edition)
Channel Formation
VGS ≥Vt Channel formation takes place
 Uniform channel if VDS=0 i.e., uniform depth from
Drain to Source end.
 With increasing V , depletion region width also
GS
increase

Source: CMOS Digital Integrated Circuit, Sung & Yusuf, 3rd

edition)
Linear mode
VDS=Moderate, VGS ≥Vt
Channel depth non-zero at Drain end.
VDS <VGS-VT  VDS < VOV

Source: CMOS Digital Integrated Circuit, Sung & Yusuf, 3rd

edition)
Edge of Saturation
• Pinch-off or Onset of Saturation
• Channel depth Zero at Drain end.
• VGS ≥Vt, VDS =VGS-VT  VDS = VOV

Source: CMOS Digital Integrated Circuit, Sung & Yusuf, 3rd

edition)
Beyond Saturation
• Strong Saturation-
• VGS ≥Vt, VDS >VGS-VT  VDS > VOV
• Channel shrink toward Source end with
increasing VDS

Source: CMOS Digital Integrated Circuit, Sung & Yusuf, 3rd

edition)
Drain characteristics

Source: Microelectronics, Sedra & Smith, 6 th

edition)
CMOS inverter
CMOS inverter
Equivalent circuit
CMOS inverter
VTC of CMOS
Transistor symbols and switch-level
models

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E.
Weste and David Money Harris
 CMOS Logic
 CMOS Inverter
 Combination of nMOS and pMOS

Truth table
Y = A’
Logic diagram Symbol and
boolean
expression

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste
and David Money Harris
Two input CMOS NAND Gate

Symbol and boolean

Logic diagram expression

Truth table
Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E.
Weste and David Money Harris
Connection and behavior of series and parallel
transistors

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil
H. E. Weste and David Money Harris
Two input NOR Gate

Symbol and boolean

Truth table expression
Logic
diagram

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E.
Weste and David Money Harris
 Compound Gates
 Implements more complex functions
 Y = (A · B) + (C · D)

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil
H. E. Weste and David Money Harris
Compound Gates
 Y = (A + B + C) · D

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste
and David Money Harris
MOS Fabrication steps
Oxidation of silicon substrate
NMOS Fabrication steps
CMOS Fabrication
CMOS Inverter cross-section with
well and substrate contacts

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E.
Weste and David Money Harris
Steps of fabrication:
1. Start with p-type silicon wafer
 consists of a series of steps in which layers of the chip are defined
through a process called photolithography.
 The process begins with the creation of an n-well on a bare p-type silicon
wafer.

 Forming the n-well requires adding enough Group V dopants into the
silicon substrate to change the substrate from p-type to n-type in the
region of the well.

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E.
Weste and David Money Harris
 To define n-wells, a protective layer of oxide layer grown over the
entire wafer,
 Then removal of oxide layer where we want the wells
 Growing of oxide layer--The wafer is first oxidized in a high-temperature
(typically 900–1200 °C) furnace --causes Si and O2 to react and
become SiO2 on the wafer surface

 The oxide must be patterned to define the n-well

 Growing of photoresist layer

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste and David Money Harris
An organic photoresist2 that softens where
exposed
 to light is spun onto the wafer
The photoresist is exposed through the n-well
mask that allows light to pass through only where
the well should be
The softened photoresist is removed to expose the
oxide

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste and
David Money Harris
 The well is formed where the substrate is not covered with oxide. Two ways to add
dopants are diffusion and ion implantation
 In the diffusion process, the wafer is placed in a furnace with a gas containing the
dopants. When heated, dopant atoms diffuse into the substrate.
 With ion implantation, dopant ions are accelerated through an electric field and blasted
into the substrate. In either method, the oxide layer prevents dopant atoms from entering
the substrate where no well is intended. Finally, the remaining oxide is stripped with HF
to leave the bare wafer with wells in the appropriate places.

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste and
David Money Harris
 The transistor gates are formed next.
 These consist of polycrystalline silicon, generally
 called polysilicon, over a thin layer of oxide. The thin oxide is grown in a furnace. Then
the wafer is placed in a reactor with silane gas (SiH4) and heated again to grow the
polysilicon layer through a process called chemical vapor deposition. The polysilicon is
heavily doped to form a reasonably good conductor.

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste and
David Money Harris
 The n+ regions are introduced for the transistor active area and the well contact. As with
the well, a protective layer of oxide is formed

 patterned with the n-diffusion mask to expose the areas where the dopants are needed

 N+ diffusion and n well contact

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste and
David Money Harris
 P+ diffusion and p-substrate contact

 The field oxide is grown and contact cuts are defined where metal should attach to
diffusion or polysilicon

 Finally, aluminum sputtered over the entire wafer, filling the contact
cuts as well

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste and
David Money Harris
Complete fabricated structure of CMOS

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste and
David Money Harris
Stick diagram
Stick Diagrams
 Stick diagrams represents layer information using simple
diagrams.
 layer information is conveyed through color codes (or
monochrome encoding).
 Acts as an interface between symbolic circuit and the actual
layout
Stick Diagrams Notations

Source: https://www.researchgate.net/publication/324006365_Stick_Diagram
 Stick Diagrams Rules
 Rule 1: When two or more ‘sticks’ of the same type cross or touch each other that represents
electrical contact.

 Rule 2: When two or more sticks of different type cross or touch each other there is no
electrical contact. (If electrical contact is needed we have to show the connection explicitly)

Source: https://www.researchgate.net/publication/324006365_Stick_Diagram
 Stick Diagrams Rules
 Rule 3: When a poly crosses diffusion it represents a transistor
Note: If a contact is shown then it is not a transistor

Source: https://www.researchgate.net/publication/324006365_Stick_Diagram
 Stick Diagrams Rules
 Rule 4: In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All
PMOS must lie on one side of the line and all NMOS will have to be on the other side.

Source: https://www.researchgate.net/publication/324006365_Stick_Diagram
Example of Stick Diagrams: CMOS
inverter

Source: https://www.researchgate.net/publication/324006365_Stick_Diagram
Stick diagram for NAND gate using CMOS logic
Stick diagram for NAND gate using CMOS
logic VDD

GND
Stick diagram for NAND gate using CMOS logic
VDD

G
D S D S

D S D S

G
G
GND
 Stick diagram for NAND gate using CMOS logic VDD
G G
D S D S

N-Well

PMOS
Logic D S D S

G
G
NMOS
Logic
GND
 Stick diagram for NAND gate using CMOS logic VDD
G G
D S D S

A B
N-Well
PMOS Vout
Logic
S D S
D

G
G
NMOS
Logic
GND
Stick diagram for NOR gate using CMOS logic VDD

GND
 Stick diagram for NOR gate using CMOS logic
VDD

G
S S D
D

S D D S

G
G
GND
 Stick diagram for NOR gate using CMOS logic VDD
G G
S D S D

A B
N-Well
Vout
PMOS
Logic
S D
D S

G
G
NMOS
Logic
GND
Example of Stick Diagrams: NOR gate

Source: https://www.researchgate.net/publication/324006365_Stick_Diagram
 Stick diagrams limitations
Does not show

 Exact placement of components

 Transistor sizes – Wire lengths, wire widths, tub boundaries –
 Any other low level details such as parasitics

Source: https://www.researchgate.net/publication/324006365_Stick_Diagram
 Layout
 Representation of an integrated circuit in terms of planar
geometric shapes
Correspond to the patterns of metal, oxide, or semiconductor
layers that make up the components of the integrated circuit.
Layout design rules
 Layout design rules describe how small features can be and how closely they can be
reliably packed in a particular manufacturing process
 Industrial design rules are usually specified in microns.
 Migrating from one process to a more advanced process or a different foundry’s
process is difficult in microns rule.
 Layout design rules
 Mead and Conway [Mead80] popularized scalable design rules based on a single parameter, λ.

 λ is generally half of the minimum drawn transistor channel length

 Channel length is the distance between the source and drain of a transistor and is set by the
minimum width of a polysilicon wire

 For example, a 180 nm process has a minimum polysilicon width (and hence transistor
length) of 0.18 µm and uses design rules with λ = 0.09µm
 Layout design rules
 Metal and diffusion have minimum width and spacing of 4 λ.

 Contacts are 2 λ × 2 λ and must be surrounded by 1 λ on the layers above and below.
 Distance between two contacts-- 3 λ

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste and
David Money Harris
 Layout design rules
 Polysilicon uses a width of 2 λ

 N-well surrounds pMOS transistors by 6 λ and avoids nMOS transistors by 6 λ.

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste and
David Money Harris
Layout of CMOS inverter

CMOS
inverter
Layout

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste and
David Money Harris
Layout of Three input NAND gate

Three input NAND Layout

gate
Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E. Weste and
David Money Harris
Layout Design of an Inverter
 Layout Design of an Inverter

2λ

Polysilicon
layer
 Layout of NMOS Transistor

Diffusion
area
(Source/
Drain)
 Lambda rule for NMOS
2λ

Metal contact or 1.5λ

Active area 2λ 2λ 2λ 1.5λ
contact 2λ
Or diffusion area 1.5λ 1.5λ
contact

Poly contact or 2λ
Gate contact
 Layout of PMOS Transistor
10
λ
2λ N-
Well

1.5λ
Metal contact or 2λ 2λ 2λ 2λ 1.5λ
Active area contact
Or diffusion area 1.5λ 1.5λ
contact

Poly 2λ
contact or
Gate
contact
 10λ

N-Well
Metal 3λ
Layer
Layer

2λ 2λ

2λ

Metal contact in PMOS Transistor

Step 1- Create Vdd and Gnd layer
VDD 3λ

Gnd 3λ
Step 2- Place the transistor
VDD
2λ
2λ
3λ Active area

Poly silicon
Layer

3λ Active area
2λ
2λ
Gnd
Step 3- Create contacts
VDD

2λ
2λ
Active metal
contact

Poly metal
contact

Gnd
Step 4- complete the wire connection
VDD

Sourc Drai
e n

Gate

Source Drai
n

Gnd
 VDD

Vin
6λ Vout

Gnd
Layout for NAND Gate
Step 1- Create Vdd and Gnd layer
VDD 3λ

Gnd 3λ
Layout for NAND Gate
VDD 3λ

Gnd 3λ
Layout for NAND Gate
VDD 3λ

3λ

3λ

2λ 2λ
Gnd 3λ
Layout for NAND Gate
VDD 3λ

D S S D
3λ

Vout
A B

3λ

S D S D
2λ 2λ
Gnd 3λ
Design Flow
Alternative way
Y Chart

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E.
Weste and David Money Harris
 Logic Design
 We specify the logic with Hardware Description Language (HDL), which
provides a higher level of abstraction than schematics or layout.
 This code is often called the Register Transfer Level (RTL) description.
 8-bit adder as a ripple carry adder composed of eight cascaded full
adders.

Full adder

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E.
Weste and David Money Harris
 Circuit Design
 Circuit design is concerned with arranging transistors to perform a
particular logic function
 The circuit can be represented as a schematic, or in textual form as a
netlist.
 Common transistor level netlist formats include Verilog and SPICE.
 Verilog netlists --used for functional verification,
 SPICE netlists --necessary for delay and power simulations.

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E.
Weste and David Money Harris
 Physical Design
 Physical design begins with a floorplan

 Essential to determine whether a proposed design will

fit in the chip area budgeted

 Used to estimate wiring lengths and wiring congestion

 Design Verification
 Design verification is essential to catching the errors before
manufacturing and commonly accounts for half or more of the effort
devoted to a chip

 A testbench is used to verify that the logic is correct

 Layout vs. Schematic tools (LVS) check that transistors in a

 Layout are connected in the same way as in the circuit schematic.

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E.
Weste and David Money Harris
Fabrication
Fabrication requires many deposition, masking,
etching,
and implant steps.
Multiple chips are manufactured simultaneously
on a single silicon wafer
Integrated circuit fabrication plants (fabs) now
cost billions of dollars And become obsolete in a
few years.
Fabrication
An engineer in a clean room holding
a completed 300 mm wafer.
Clean rooms are filtered to eliminate most
dust
And other particles that could damage
a partially processed wafer

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E.
Weste and David Money Harris
Packaging
Processed wafers are sliced into dice (chips) and
packaged
This wire-bonded package uses thin goldwires to
connect the pads on the die

Chip in a 40-pin dual-inline

package

Source: CMOS VLSI Design, A Circuits and Systems Perspective, Pearson, Fourth Edition, Neil H. E.
Weste and David Money Harris
Testing
Even tiny defects in a wafer or dust particles can
cause a chip to fail
Chips are tested before being sold
Testers capable of handling high-speed chips cost
millions of dollars
many chips use built-in self-test features to
reduce the tester time required
Thank You