COMPUTER ORGANIZATION

Text Book:
Carl Hamacher, ZvonkoVranesic, SafwatZaky, Computer
Organization, 5th Edition, Tata McGraw Hill.

Dept of CSE
 COMPUTER ORGANIZATION
4. Input/Output Organization
• Accessing I/O Devices.

• Interrupts – Interrupt Hardware.

• Enabling and Disabling Interrupts.

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• Handling Multiple Devices.

• Direct Memory Access:

• Bus Arbitration, Speed, size and Cost of memory

systems.

• Cache Memories – Mapping Functions.

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 Accessing I/O Devices

• A simple arrangement to connect 1/0 devices to a computer is to

use a single bus arrangement, as shown in Figure.
• The bus enables all the devices connected to it to exchange
information.
• Typically, it consists of three sets of lines used to carry address,
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data, and control signals. Each I/O device is assigned a unique set
of addresses.
• When the processor places a particular address on the address
lines, the device that recognizes this address responds to the
commands issued on the control lines.
• The processor requests either a read or a write operation, and the
requested data are transferred over the data lines.
 Accessing I/O Devices

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Fig: A Single bus Structure.

 Memory-Mapped I/O
• When I/O devices and the memory share the same
address space, the arrangement is called memory
mapped I/O.
• With memory-mapped I/O, any machine instruction
that can access memory can be used to transfer
data to or from an I/O device.
Dept of CSE • Most computer systems use memory-mapped I/O.
• Some processors have special IN and OUT
instructions to perform I/O transfers.
• When building a computer system based on these
processors, the designer has the option of
connecting I/O devices to use the special I/O
address space or simply incorporating them as part
of the memory address space.
 I/O Interface for an Input
Devicedecoder, the data and status
The address
registers, and the control circuitry required to
coordinate I/O transfers constitute the device’s
interface circuit.

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 I/O Technique
Programmed

Interrupt driven

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Direct Memory Access (DMA)
 Program-Controlled I/O
• Consider a simple example of I/O operations
involving a keyboard and a display device in a
computer system. The four registers shown below
are used in the data transfer operations.
• The two flags KIRQ and DIRQ in STATUS register are
used in conjunction with interrupts.
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 An Example
A program that reads one line from the keyboard,
stores it in memory buffer, and echoes it back to
the display.

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 Program-Controlled I/O
The example described above illustrates program
controlled I/O, in which the processor repeatedly checks a
status flag to achieve the required synchronization
between the processor and an input or output device. We
say that the processor polls the devices
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There are two other commonly used mechanisms for
implementing I/O operations: interrupts and direct memory
access

Interrupts: synchronization is achieved by having the I/O

device send a special signal over the bus whenever it is
ready for a data transfer operation
Direct memory access: it involves having the device
 Interrupts
To avoid the processor being not performing any
useful computation, a hardware signal called an
interrupt to the processor can do it. At least one of
the bus control lines, called an interrupt-request
line, is usually dedicated for this purpose.

Dept of CSE An interrupt-service routine usually is needed and is

executed when an interrupt request is issued

On the other hand, the processor must inform the

device that its request has been recognized so that
it may remove its interrupt-request signal.
An interrupt-acknowledge signal serves this function
 Example

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 Interrupt-Service Routine &
 Subroutine
Treatment of an interrupt-service routine is very similar to
that of a subroutine

• An important departure from the similarity should be noted

• A subroutine performs a function required by the program
from which it is called.
Dept of CSE • The interrupt-service routine may not have anything in
common with the program being executed at the time the
interrupt request is received. In fact, the two programs
often belong to different users

 Before executing the interrupt-service routine, any

information that may be altered during the execution of
that routine must be saved. This information must be
restored before the interrupted program is resumed.
 Interrupt Latency
The information that needs to be saved and restored
typically includes the condition code flags and the
contents of any registers used by both the interrupted
program and the interrupt-service routine

Saving registers also increases the delay between the

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execution of the interrupt-service routine. The delay is
called interrupt latency

Typically, the processor saves only the contents of the

program counter and the processor status register. Any
additional information that needs to be saved must be
saved by program instruction at the beginning of the
 Interrupt Hardware
An equivalent circuit for an open-drain bus used to
implement a common interrupt-request line.

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 ENABLING AND DISABLING INTERRUPTS
• The arrival of an interrupt request from an external device causes the processor
to suspend the execution of one program and start the execution of another.
Because interrupts can arrive at any time, they may alter the sequence of
events from that envisaged by the programmer.
• Hence, the interruption of program execution must be carefully controlled. A
fundamental facility found in all computer is the ability to enable and disable
such interruptions as desired.
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Let us consider in the specific case of a single interrupt request from one device.
• When a device activates the interrupt-request signal, it keeps this signal
activated until it learns that the processor has accepted its request. This means
that the request signal will be active during execution of the interrupt-service
routine, perhaps until an instruction is reached that accesses the device in
question.
• It is essential to ensure that this active request signal does not lead to
successive interruptions, causing the system to enter an infinite loop from
which it cannot recover.
 ENABLING AND DISABLING INTERRUPTS
several ways to address the these issues
 The first possibility is to have the processor hardware ignore interrupt-request
line until the execution of first instruction of the interrupt-service routine has
been completed. Then, by using an Interrupt-disable instruction as
the first instruction in the routine, the programmer can ensure that no further
interruptions will occur until an Interrupt-enable instruction is executed.

 The second option, which is suitable for a simple processor with only on
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interrupt- request line, is to have the processor automatically disable interrupts
before starting the execution of the interrupt-service routine. After saving the
contents of the and the processor status register (PS) on the stack, the processor
performs the equivalent of executing an Interrupt-disable instruction.

 In third option, the processor has a special Interrupt-request line or which the
interrupt-handling circuit responds only to the leading edge of the signal. Such a
line is said to edge-triggered. In this case, the processor will receive only one
request, regardless of how long the line is activated.
 ENABLING AND DISABLING INTERRUPTS
The sequence of events involved in handling an interrupt request from a
single device. Assuming that interrupts are enabled, the following is a
typical scenario:

1. The device raises an interrupt request.

2. The processor interrupts the program currently trying executed.
Dept of CSE 3.Interrupts are disabled by changing the control bits in the PS (except in
the case of edge-triggered interrupts).
4. The device is informed that its request has been recognized, and in
response, it deactivates the interrupt-request signal.
5.The action requested by the interrupt is performed by the interrupt-
service routine.
6.Interrupts are enabled and execution of the interrupted is resumed.
 Handling Multiple Devices

 Handling multiple devices gives rise to a number

of questions
• How can the processor recognize the device requesting an
interrupt?
• Given that different devices are likely to require different interrupt-
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service routines, how can the processor obtain the starting
address of the appropriate routine in each case?
• Should a device be allowed to interrupt the processor while
another interrupt is being serviced?
• How should two or more simultaneous interrupt request be
handled?
 The information needed to determine whether a device
is requesting an interrupt is available in its status
register
 Identify the Interrupting
• The Device
simplest way to identify the interrupting device
is to have the interrupt-service routine poll all the I/O
devices connected to the bus
• The polling scheme is easy to implement. Its main
disadvantage is the time spent interrogating all the devices
• A device requesting an interrupt may identify itself
Dept of CSE directly to the processor. Then, the processor can
immediately start executing the corresponding
interrupt-service routine. This is called vectored
interrupts
• An interrupt request from a high-priority device
should be accepted while the processor is servicing
another request from a lower-priority device
 Interrupt Priority
 The processor’s priority is usually encoded in a few
bits of the processor status word. It can be changed by
program instructions that write into the program status
register (PS). These are privileged instructions, which
can be executed only while the processor is running in
the supervisor mode
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 The processor is in the supervisor mode only when

executing operating system routines. It switches to the
user mode before beginning to execute application
program

 An attempt to execute a privileged instruction while in

the user mode leads to a special type of interrupt
 Implementation of Interrupt
Priority
An example of the implementation of a multiple priority
scheme

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 Simultaneous Requests
• Consider the problem of simultaneous arrivals of
interrupt requests from two or more devices. The
processor must have some means of deciding which
request to service first
• Interrupt priority scheme with daisy chain

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 Priority Group
Combination of the interrupt priority scheme with daisy
chain and with individual interrupt request and interrupt
acknowledge lines.

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