MIT-WPU

School of Electronics and Communication Engineering

S.Y. B. Tech (SEM- IV)
Microcontroller and Applications
ECE2003B
Dr. Manisha Kowdiki
Course Content
1. Introduction to Microcontroller

2. CIP-51 Architecture

3. Peripheral Interfacing and Programming-I

4. Peripheral Interfacing and Programming-II

Course Objectives & Course Outcomes :

Pre-requisites: Exposure to Digital Electronics

Course Objectives:
1. Knowledge:
• Basics of Microprocessor and Microcontroller architecture and features
• Integrated Development Environment (IDE) for developing microprocessor and
microcontroller-based applications.
• Interfacing of a microcontroller with various peripherals.

2. Skills:
• To write assembly language and embedded C programs.
• To apply knowledge for the development of multidisciplinary projects.

3.Attitude:
• To select the appropriate microcontroller for the desired application.
• To develop real-world applications using a microcontroller.
Course Objectives & Course Outcomes :

Course Outcomes: After completion of this course students will be able to

1. Explain the architecture of the microcontroller (CL-II)

2. Make use of Integrated Development Environment (IDE) for programming and debugging.
(CL-III)

3. Apply knowledge of microcontroller interfacing with various peripherals for developing

real-world applications. (CL-III)
4. Compare various microcontrollers and select the appropriate microcontroller for the desired
application. (CL-IV)
Syllabus:

• Introduction to Microcontroller: Microprocessor and Microcontroller comparison, Microcontroller

architecture comparison, Role of microcontroller in Embedded System, Introduction to CIP-51 architecture
and block diagram,, Instruction set, and Assembly language programming.

• CIP-51 Architecture: Reset sources, Oscillator options, Memory Organization, Port structure, Timers,
Timer programming, Interrupt handler, Power management modes. (All programs in Embedded C).

• Peripheral Interfacing and Programming-I: Interfacing of LED, Relay, Buzzer, Switch, 7-segment
display, LCD, Keypad, Stepper Motor, DAC ADC programming, Programmable Counter Array (PCA), DC
motor control using PWM (All programs in Embedded C).

• Peripheral Interfacing and Programming-II: Basics of Serial Communication protocol:UART, study of

RS 232,RS 485, I2C, and SPI (All programs in Embedded C), Comparative study of various emerging
microcontrollers, Microcontroller application Case Study.
 Laboratory Exercises / Practical:
List of Practical:
1. Simple assembly language programming.

2. Complex assembly language programming.

3. Interfacing LED, Relay, Buzzer, and switch with C8051F340.

4. Interfacing LCD with C8051F340.

5. Interfacing DAC with C8051F340.

6. Interfacing ADC with C8051F340.

7. Interfacing DC motor and control its speed using PWM with C8051F340.

8. Interfacing UART with C8051F340.

9. Interfacing Stepper Motor with C8051F340.

10.Interfacing EEPROM using SPI with C8051F340.

11. Design and implement a microcontroller-based project.

Course Evaluation

• CCA- 30 Marks:
✔Assignment(15M)+
✔Midterm(15M)

• LCA- 30 Marks:
✔Expt -10Marks +
✔Midterm Exam 10Marks+
✔Endterm 10M

• End Term– 40 Marks

 UNIT-I
Introduction to Microcontroller

Part 1
Contents
• Microprocessor and Microcontroller comparison,

• Microprocessors and microcontroller architecture comparison

• Role of microcontroller in Embedded System

• Introduction to CIP-51 architecture and block diagram

• Memory organization

• Instruction set

• Assembly programming
Terminologies:
• Integrated Circuit (IC): A miniaturized electronic circuit that consists of
semiconductor devices and passive components contained in a package.

• Central Processing Unit (CPU): This refers to the core of the MCU that
executes code

• Microcontroller Unit (MCU): This is the standard acronym used for

microcontrollers, and refers to the full IC that contains the CPU and peripherals.

• “n-bit” – the “n” refers to the data bus width of the CPU, and is the maximum
width of data it can handle at a time
• Examples: 8-bit MCU, 32-bit MCU
Micro-processors and Microcontrollers

• Microprocessor: General-purpose CPU/ General-purpose Processor (GPP)

• Emphasis is on flexibility and performance
• Generic user-interface such as keyboard, mouse, etc.
• Used in a PC, PDA, cell phone, etc.

• Microcontroller: Microprocessor + Memory on a single chip

• Emphasis is on size and cost reduction
• The user interface is tailored to the application, such as the buttons on a TV remote
control
• Used in a digital watch, TV remote control, car and many common day-to-day
appliances
Microprocessor Vs Microcontroller
Microprocessor Vs Microcontroller
Microprocessor Vs Microcontroller
Microprocessor Microcontroller
1 It is only a processor, so memory and I/O Micro Controller has a processor along with internal
components need to be connected externally and memory and I/O components and having lower power
having higher power consumption consumption

2. Memory and I/O has to be connected externally, Memory and I/O are already present, and the internal
so the circuit becomes large. circuit is small.
3. Microprocessors are based on Von Neumann Micro controllers are based on Harvard architecture
model
4 High Processing Power in terms of instruction Low processing Power in terms of instruction
execution(MIPS) execution(MIPS)
5 CPU word size can be 16/ 32/64 bit CPU word size can be 8/16/32 bit
6 It has no RAM, ROM, Input-Output units, timers, It has a CPU along with RAM, ROM, and other
and other peripherals on the chip. peripherals embedded on a single chip.
7 It’s used for general purpose It’s used for application-specific systems.
applications that allow you to handle loads of data
Microprocessor Vs Microcontroller
Microprocessor Microcontroller
General purpose Processor Application specific
Bulkier and Expensive A single chip and cost effective
High computing power Can perform limited calculations
More power consumption Less power consumption
Only word/ byte transferable Also bit transferable
Pins are fixed Port pins are programmable
Very fast (> 1GHz) Relatively slow (typically 10-
20MHz) since most I/O devices
being controlled are relatively slow.
Eg. Intel 8085, 8086, Motorola’s Eg. Intel’s MCS-51, Atmel’s AT89c51
680x
https://raspberrytips.com/is-raspberry-pi-a-microcontroller/
Role of microcontroller in Embedded System
• A combination of hardware and software designed to perform a dedicated
function
• Embedded systems are computing systems with tightly coupled hardware and
software integration.
• Designed to perform dedicated function
• Embedded systems are part of a larger system or product,
-e.g., antilock braking system in a car (The anti-lock braking system
means the system that prevents the wheels from locking when the brakes are
applied in a moving car. )
• Embedded systems are tightly coupled to their environment 🡪 imposes real-
time constraints by the need to interact with the environment
Embedded Products Using Microcontrollers (Applications)
• Home
• Appliances, intercom, telephones, security systems, garage door openers, answering
machines, fax machines, home computers, TVs, cable TV tuner, VCR, camcorder,
remote controls, video games, cellular phones, musical instruments, sewing machines,
lighting control, paging, camera, pinball machines, toys, exercise equipment
• Office
• Telephones, computers, security systems, fax machines, microwave, copier, laser
printer, color printer, paging
• Auto
• Trip computer, engine control, air bag, instrumentation, security system, transmission
control, entertainment, climate control, cellular phone, keyless entry
Is 8-bit Still Relevant?
• “n-bit” – the “n” refers to the data bus width of the CPU, and is the
maximum width of data it can handle at a time.

• 8-bit microcontrollers are sufficient and cost-effective for many embedded

applications

• More and more advanced features and peripherals are added to 8-bit
processors by various vendors

• 8-bit MCUs are well-suited for low-power applications that use batteries.
8-bit MCUs tend to be easier to program and understand on a
deep level compared to 32-bit.
The 8051 Microcontroller—A Brief History
• In 1980, Intel introduced the 8051, relevant today after more than two
decades
• First device in the MCS-51® family of 8-bit microcontrollers
• In addition to Intel there are other second source suppliers of the ICs, who
make microcontrollers that are compatible with the 8051 architecture.
• In recent years some companies have incorporated many different and
additional features into 8051
• In 2000, Silicon Laboratories introduced CIP-51 microcontroller chip
(C8051F340) based on the 8051 core CPU
• Silicon Labs is a leading manufacturer of 8051 based microcontroller.
https://www.manualslib.com/manual/152880/Silicon-Laboratories-C8051f341.html?
page=73#manual
Von Neumann and Harvard architecture
• Von Neumann Architecture: It is a digital computer architecture whose design is based
on the concept of stored program computers where program data and instruction data
are stored in the same memory.

• This architecture was designed by the famous mathematician and physicist John Von
Neumann in 1945.

• Harvard Architecture: It is the digital computer architecture whose design is based on

the concept where there are separate storage and separate buses (signal path) for
instruction and data.

• It was basically developed to overcome the bottleneck of Von Neumann Architecture.

Von Neumann and Harvard architecture Output Unit: Monitor,
Input Unit: Keyboard, mouse, Printer, plotter, Speaker
Joystick, camera, scanner

Each location of the memory has

unique address, .
Execution of instruction is carried
out sequentially.
Comparison of Von Neumann and Harvard
Von Neumann architecture Harvard architecture

1. Fetches Instruction and Data from two separate memory spaces

2. Processor needs 1 clock cycles to execute instruction
1. Fetches instructions and data from a single memory space 3. Control unit for 2 buses is more complicated & increases the
2. Processor needs 2 clock cycles to execute instruction. development cost
3. Simpler control unit design & development of 1 is cheaper & faster. 4. Data transfer & instruction fetches can be performed at the same
4. Data transfer & instruction fetches cannot be performed time.
simultaneously. 5. Improved operating bandwidth
5. Limits operating bandwidth
6. Allows for different bus widths
6. Allows for fixed bus widths
7. Architecture --- RISC
7. Architecture --- CISC
8. Fixed instruction format
8. Variable instruction format
9. As data bus & address bus are separate, faster flow of data flow thro
9. Data flow & Speed of work is less comparatively. CPU and greater speed of work
10. Used in personal computers, laptop & workstations. 10. Used in microcontrollers & signal processing.
RISC (Reduced Instruction Set Computer):
• The RISC processors have a comparatively smaller set of instructions along with few addressing nodes.
• The fundamental goal of RISC is to make hardware simpler by employing an instruction set that
consists of only a few basic steps used for evaluating, loading, and storing operations.
• A load command loads data but a store command stores data.

CISC (Complex Instruction Set Computer):

• The CISC processors consist of a larger set of instructions along with multiple addressing nodes.
• The fundamental goal of CISC is that a single instruction will handle all evaluating, loading, and storing
operations.

Both CISC and RISC approaches primarily try to increase the performance of a CPU.
Here is how both of these work:
1. CISC: This kind of approach tries to minimize the total number of instructions per program, and it does
so at the cost of increasing the total number of cycles per instruction.
2. RISC: It reduces the cycles per instruction and does so at the cost of the total number of instructions per
program.
RISC Vs CISC Sr.
: Properties RISC (Reduced Instruction CISC (Complex
No. Set Computer) Instruction Set Computer)
1 No. of Instructions Less More
2 Addressing Modes Less More
3 Instruction Formats Less More
4 Instruction Size Fixed Variable
5 Control Unit Hardwired Micro-programmed
6 No. of Bus Cycles to Single CPU cycle (for 80% Multiple CPU cycles
execute an instruction Instructions)
7 Control Logic & Simple Complex
Decoding Subsystem
8 Pipelining Huge no. of stages of Difficulty in efficient
Pipelining implementation
9 Design time & Smaller time & less probable Long time & Significant
Probability of Design probability
Errors
10 Complexity of Compiler Simpler More complex
11 HLL(High level Supported Not supported
language) Instructions

* A pipeline is the mechanism a RISC processor uses to execute instructions. Using a pipeline speeds up execution by fetching the next
instruction while other instructions are being decoded and executed.
 RISC vs. CISC
RISC (Reduced Instruction Set Computer) CISC (Complex Instruction Set Computer )

1. Simple Instruction taking 1 cycle 1. Complex Instruction taking multiple cycles

2. Only LOADs, STOREs access memory 2. Any Instruction may access memory

3. Designed around pipeline* 3. Designed around Instruction Set

4. Instruction executed by h/w 4. Instruction interpreted by micro program

5. Fixed format Instruction 5. Variable format Instruction

6. Few Instruction and modes 6. Many Instruction and modes

7. Complexity in the compiler 7. Complexity in the micro program

8. Multiple register sets 8. Single register set

9. Operates at 50-150 MHz 9. Operates at 33-50 MHz

* A pipeline is the mechanism a RISC processor uses to execute instructions. Using a pipeline speeds up execution by fetching the next
instruction while other instructions are being decoded and executed.
 Concept of Pipeline
Fetch
Decode
Execute
Features of C8051F340 AT A GLANCE
 What is the highest speed the micro controller supports

Does it comes in 40-pin DIP (Dual inline package) or QFP (Quad flat package)

Critical for battery powered products

Important in terms of final cost of the product in which MC is used

How easy it is to develop product around it.
Its ready availability in needed quantities both now & in the future.
MCU: A microcontroller unit (MCU) is a compact integrated circuit designed to govern a specific operation in an
embedded system.
A typical microcontroller includes a processor, memory and input/output (I/O) peripherals on a single chip.

• The MCU system controller core is the CIP-51 microcontroller.

• The CIP-51 is fully compatible with the MCS-51™ instruction set;
• Standard 803x/805x assemblers and compilers can be used to develop software.
• The MCU family has a superset of all the peripherals included with a standard 8051.
• Included are four 16-bit counter/timers (see description in Section 21),
• An enhanced full-duplex UART (see description in Section 18),
• An Enhanced SPI (see description in Section 20),
• 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space (Section 9.2.6),
• 5 Port I/O (see description in Section 15).
• The CIP-51 also includes on-chip debug hardware (see description in Section 23), and interfaces
directly with the analog and digital subsystems providing a complete data acquisition or control-
system solution in a single integrated circuit.
• The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well
as additional custom peripherals and functions to extend its capability (see Figure 9.1 for a block
diagram).
Thin quad flat pack (TQFP)
Introduction to CIP-51 architecture
The CIP-51 includes the following features:

• The CIP-51 employs a pipelined architecture

• Fully Compatible with MCS-51 Instruction Set
• 0 to 48 MHz Clock Frequency
• 256 Bytes of Internal RAM
• 5 Port I/O
• Extended Interrupt Handler
• Reset Input
• Power Management Modes
• On-chip Debug Logic
• Program and Data Memory Security
Block Diagram C8051F340
C8051F340 Highlighted Features
▪ High-speed pipelined 8051-compatible microcontroller core (up to 48 MIPS)
(Million instructions per second (MIPS) is an approximate measure of a computer's raw processing power.)
▪ In-system, full-speed, non-intrusive debug interface (on-chip) [I ntrusive debug may be anything that affects Size and
speed. ]
▪ Universal Serial Bus (USB) Function Controller
▪ True 10-bit 200 ksps differential / single-ended ADC with analog multiplexer
▪ On-chip Voltage Reference and Temperature Sensor
▪ On-chip Voltage Comparators (2)
▪ Precision internal calibrated 12 MHz internal oscillator and 4x clock multiplier
▪ Internal low-frequency oscillator for additional power savings
▪ Up to 64 kB of on-chip Flash memory
▪ Up to 4352 Bytes of on-chip RAM (256 +4096 bytes (4 kB)
▪ External Memory Interface (EMIF) available on 48-pin versions.
▪ SMBus/I2C, up to 2 UARTs, and Enhanced SPI serial interfaces implemented in hardware
▪ Four general-purpose 16-bit timers
▪ Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer
function
▪ On-chip Power-On Reset, VDD Monitor, and Missing Clock Detector
▪ Up
I2C: to 40 Port I/O
inter-integrated (5 Ports, each port of 8pins)
controller.
SMBus:The System Management Bus
Performance of C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D:
• The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture.
• In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and
usually have a maximum system clock of 12 MHz.
• By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions
taking more than eight system clock cycles
• With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS.
• The CIP-51 has a total of 109 instructions.
• The table below shows the total number of instructions that for execution time:
Micro Controller performs all operations in hex
9.2. Memory Organization of C8051F340 (Will be referred again in unit 2)
• The memory organization of the CIP-51 System Controller is similar to that of a standard 8051.
• There are two separate memory spaces: Program memory and Data memory.
• Program and data memory share the same address space but are accessed via different instruction types.
1. Program Memory(PG): The CIP-51 core has a 64k-byte PM space.
• It has 64k(65536) bytes of this PM space as in-system, re-programmable Flash
memory.
• The addresses above 0xFBFF are reserved.
• Program memory is normally assumed to be read-only.
• However, the CIP-51 can write to PM by setting the Program Store Write Enable bit
(PSCTL.0) and using the MOVX instruction.
• This feature provides a mechanism for the CIP-51 to update program code and use the
PM space for non-volatile data storage.
2. Data Memory(DM):
• The CIP-51 includes 256 of internal RAM mapped into the DM space from
0x00 through 0xFF.
• The lower 128 bytes of data memory are used for general purpose registers and
scratch pad memory(SPRAM).
• SPRAM is a high-speed internal memory directly connected to the CPU core
and used for temporary storage to hold very small items of data .
• Either direct or indirect addressing may be used to access the lower 128 bytes of
data memory.
• Locations 0x00 through 0x1F are addressable as four banks of general purpose
registers, each bank consisting of eight byte-wide registers.
• The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as
bytes or as 128 bit locations accessible with the direct addressing mode.

3. Additional storage of 4kB

Figure 9.2. On-Chip Memory Map for 64 kB Devices
 Memory Organization of C8051F340 (Will be referred again in unit 2

Memory Classes and Layout

Memory Classes and Layout introduces the different memory types used to programming the 8051
microcontroller and variants. Memory classes identify distinct physical memory regions, which can be
represented in a memory layout. Physical memory regions in an A51 system include:

Program Memory: in the classic 8051, this is a 64KB space called CODE. Typically, this region is a ROM
space that used for the program code and constants. Constants are fetched with the MOVC instruction.

Internal Data Memory: in the classic 8051, this is the on-chip RAM space with a maximum of 256 Bytes
containing register banks, BIT space, direct addressable DATA space, and indirect addressable IDATA space.
This region should be used for frequently used variables.

External Data Memory: in classic 8051 devices, this area, called XDATA, is off-chip RAM with a space of up
to 64KB.
However, several new 8051 devices have additional on-chip RAM that is mapped into the XDATA space.
Usually, this additional on-chip RAM has to be enabled via dedicated SFRs.
 9.2.7. Register Descriptions

• Registers are tools used for programming.

• The R0 to R7 registers are used to store ordinary vaues. So (R0-R7) x4 Reg. Banks = 32 general purpose registers.
• These are of 8 bits.
• The Accumulator, R0–R7 registers and B register are 1-byte value registers
• There are other types of registers used for special use & called Special Function Register (SFR).
Ex: ADD, PSW, P0-P4:Port latches, SP, DPTR, C, TCON, SCON, …PCON…
• The Data Pointer (DPTR) is the only user-accessible 16-bit (2-byte) register.
• DPTR is meant for pointing to data memory. As external RAM is of 16 bit, DPTR of 16 bit is used.
• It is used to access external memory using the address indicated by DPTR.
1. First 32 bytes of memory location in RAM are used as registers. (R0 to R7)

2. Register banks are selected by RS1 and RS0 bits in the program status word
 Programming using RAM location

Programming using RAM address instead of register names

It is much easier to refer to RAM locations than by their RAM address.

 9.4 Program Status Word (PSW) or Flag Register D0
D7
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CY AC FO RS1 RS0 OV UD P
Symbol Function
CY Carry flag (Carry out from the D7 bit or Bit7)
AC Auxiliary Carry flag (For BCD Operations)
If a carry is generated from D3 to D4, AC=1(SET), otherwise =0
F0 Flag 0 (Available to the user for General Purpose)
This is a bit-addressable, general purpose flag for use under software control.
RS1, Register bank select:
RS0 RS1 RS0 Working Register Bank and Address
0 0 Bank0 (Address: 00H – 07H)
0 1 Bank1 (Address:08H – 0FH)
1 0 Bank2 (D:0x10 - D:0x17 or Address: 10H – 17H)
1 1 Bank3 (D:0x18H - D:0x1F or Address: 18H – 1FH)

0V Overflow flag (The result of signed number operation is too large, causing the high-order bit to overflow into the sign bit)
This bit is set to 1 under the following circumstances: • An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases
UD User definable flag: This is a bit-addressable, general purpose flag for use under software control.
P Parity flag; P=1 for Odd no. of 1’s; P=0 for Even no. of 1’s
 Accumulator: It is used as a general register to accumulate the results of a large number of instructions.
It can hold an 8-bit (1-byte) value and is the most versatile register

The Register A is located at the address E0H in the SFR memory space.

Register A and Register B. Register A serves as an accumulator while Register B functions as a general purpose
register. These registers are used to store the output of mathematical and logical instructions.