Digital Logic Design

Gate-Level Minimization

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 3-1 Introduction
• Gate-level minimization refers to the design task of finding an optimal
gate-level implementation of Boolean functions describing a digital
circuit.

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 3-2The Map Method
• The complexity of the digital logic gates
• The complexity of the algebraic expression
• Logic minimization
• Algebraic approaches: lack specific rules
• The Karnaugh map
• A simple straight forward procedure
• A pictorial form of a truth table
• Applicable if the # of variables < 7
• A diagram made up of squares
• Each square represents one minterm

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 Review of Boolean Function
• Boolean function
• Sum of minterms
• Sum of products (or product of sum) in the simplest form
• A minimum number of terms
• A minimum number of literals
• The simplified expression may not be unique

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 Two-Variable Map
• A two-variable map
• Four minterms
• x' = row 0; x = row 1
• y' = column 0; y = column 1
• A truth table in square
diagram
• Fig. 3.2(a): xy = m3
• Fig. 3.2(b): x+y = x'y+xy' +xy
= m1+m2+m3
Figure 3.1 Two-variable Map

December 7, 2024 Figure 3.2 Representation of functions in the5map

 A Three-variable Map
• A three-variable map
• Eight minterms
• The Gray code sequence
• Any two adjacent squares in the map differ by only on variable
• Primed in one square and unprimed in the other
• e.g., m5 and m7 can be simplified
• m5+ m7 = xy'z + xyz = xz (y'+y) = xz

December 7, 2024 Figure 3.3 Three-variable Map 6

 A Three-variable Map
• m0 and m2 (m4 and m6) are adjacent
• m0+ m2 = x'y'z' + x'yz' = x'z' (y'+y) = x'z'
• m4+ m6 = xy'z' + xyz' = xz' (y'+y) = xz'

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 Example 3.1
• Example 3.1: simplify the Boolean function F(x, y, z) = (2, 3, 4, 5)
• F(x, y, z) = (2, 3, 4, 5) = x'y + xy'

Figure 3.4 Map for Example 3.1, F(x, y, z) = Σ(2, 3, 4, 5) = x'y + xy'

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 Example 3.2
• Example 3.2: simplify F(x, y, z) = (3, 4, 6, 7)
• F(x, y, z) = (3, 4, 6, 7) = yz+ xz'

Figure 3.5 Map for Example 3-2; F(x, y, z) = Σ(3, 4, 6, 7) = yz + xz'

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 Four adjacent Squares
• Consider four adjacent squares
• 2, 4, and 8 squares
• m0+m2+m4+m6 = x'y'z'+x'yz'+xy'z'+xyz' = x'z'(y'+y) +xz'(y'+y) = x'z' + xz‘ = z'
• m1+m3+m5+m7 = x'y'z+x'yz+xy'z+xyz =x'z(y'+y) + xz(y'+y) =x'z + xz = z

December 7, 2024 Figure 3.3 Three-variable Map 10

 Example 3.3

 Example 3.3: simplify F(x, y, z) = (0, 2, 4, 5, 6)

• F(x, y, z) = (0, 2, 4, 5, 6) = z'+ xy'

Figure 3.6 Map for Example 3-3, F(x, y, z) = Σ(0, 2, 4, 5, 6) = z' +xy'
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 Example 3.4
• Example 3.4: let F = A'C + A'B + AB'C + BC
a) Express it in sum of minterms.
b) Find the minimal sum of products expression.
Ans:
F(A, B, C)(1, 2, 3, 5, 7) = C + A'B

Figure 3.7 Map for Example 3.4, A'C + A'B + AB'C + BC = C + A'B
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 3.3Four-Variable Map
• The map
• 16 minterms
• Combinations of 2, 4, 8, and 16 adjacent squares

December 7, 2024 Figure 3.8 Four-variable Map 13

 Example 3.5
• Example 3.5: simplify F(w, x, y, z) = (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)

F = y'+w'z'+xz'

Figure 3.9 Map for Example 3-5; F(w, x, y, z) = Σ(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) = y' + w' z' +xz'
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 Example 3.6
• Example 3-6: simplify F = ABC + BCD + ABCD + ABC

Figure 3.9 Map for Example 3-6; ABC + BCD +

ABCD + ABC= BD + BC +ACD
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 3.4Five-Variable Map
• Map for more than four variables becomes complicated
• Five-variable map: two four-variable map (one on the top of the other).

December 7, 2024 Figure 3.12 Five-variable Map 16

 • Table 3.1 shows the relationship between the number of adjacent
squares and the number of literals in the term.

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 3-5Product of Sums Simplification

• Approach #1
• Simplified F' in the form of sum of products
• Apply DeMorgan's theorem F = (F')'
• F': sum of products → F: product of sums
• Approach #2: duality
• Combinations of maxterms (it was minterms)
• M0M1 = (A+B+C+D)(A+B+C+D') = (A+B+C)+(DD') = A+B+C

CD
AB 00 01 11 10
00 M0 M1 M3 M2
01 M4 M5 M7 M6
11 M12 M13 M15 M14
10 M8 M9 M11 M10
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 Example 3.8
 Example 3.8: simplify F = (0, 1, 2, 5, 8, 9, 10) into (a) sum-
of-products form, and (b) product-of-sums form:

a) F(A, B, C, D)=(0, 1, 2, 5,
8, 9, 10) =
B'D'+B'C'+A'C'D
b) F' = AB+CD+BD'
» Apply DeMorgan's theorem;
F=(A'+B')(C'+D')(B'+D)
» Or think in terms of maxterms

Figure 3.14 Map for Example 3.8, F(A, B, C, D)=(0,

1, 2, 5, 8, 9, 10) = B'D'+B'C'+A'C'D
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 Example 3.8 (cont.)
• Gate implementation of the function of Example 3.8

Sum-of products form Product-of sums form

Figure 3.15 Gate Implementation of the Function of Example 3.8

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 Sum-of-Minterm Procedure
• Consider the function defined in Table 3.2.
• In sum-of-minterm:

F ( x, y , z )  (1,3, 4,6)

• In sum-of-maxterm:

F ( x, y , z ) (0, 2,5,7)
• Taking the complement of F

F ( x, y , z ) ( x  z )( x  z )

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 Sum-of-Minterm Procedure
• Consider the function defined in Table 3.2.
• Combine the 1’s:

F ( x, y , z )  xz  xz 
• Combine the 0’s :

F'( x, y , z )  xz  x z 

Figure 3.16 Map for the function of Table 3.2

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 3-6Don't-Care Conditions
• The value of a function is not specified for certain combinations of
variables
• BCD; 1010-1111: don't care
• The don't-care conditions can be utilized in logic minimization
• Can be implemented as 0 or 1
• Example 3.9: simplify F(w, x, y, z) = (1, 3, 7, 11, 15) which has the
don't-care conditions d(w, x, y, z) = (0, 2, 5).

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 Example 3.9 (cont.)
• F = yz + w'x'; F = yz + w'z
• F = (0, 1, 2, 3, 7, 11, 15) ; F = (1, 3, 5, 7, 11, 15)
• Either expression is acceptable

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Figure 3.17 Example with don't-care Conditions 24
 3-7 NAND and NOR
Implementation
• NAND gate is a universal gate
• Can implement any digital system

Figure 3.18 Logic Operations with NAND Gates

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 NAND Gate
• Two graphic symbols for a NAND gate

Figure 3.19 Two Graphic Symbols for NAND Gate

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 Two-level Implementation
• Two-level logic
• NAND-NAND = sum of products
• Example: F = AB+CD
• F = ((AB)' (CD)' )' =AB+CD

December 7, 2024 Figure 3.20 Three ways to implement F = AB + CD 27

 Example 3.10
• Example 3-10: implement F(x, y, z) =

F ( x, y , z )  (1, 2,3, 4,5,7) F ( x, y , z )  xy   xy  z

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Figure 3.21 Solution to Example 3-10 28
 Procedure with Two Levels NAND
• The procedure
• Simplified in the form of sum of products;
• A NAND gate for each product term; the inputs to each NAND gate are the
literals of the term (the first level);
• A single NAND gate for the second sum term (the second level);
• A term with a single literal requires an inverter in the first level.

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 NOR Implementation
• NOR function is the dual of NAND function.
• The NOR gate is also universal.

December 7, 2024 Figure 3.24 Logic Operation with NOR Gates 30

 Two Graphic Symbols for a NOR
Gate

Figure 3.25 Two Graphic Symbols for NOR Gate

Example: F = (A + B)(C + D)E

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Figure 3.26 Implementing F = (A + B)(C + D)E 31
 Example

Example: F = (AB +AB)(C + D)

Figure 3.27 Implementing F = (AB +AB)(C + D) with NOR gates

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 Non-degenerate Forms
• 16 possible combinations of two-level forms
• Eight of them: degenerate forms = a single operation
• AND-AND, AND-NAND, OR-OR, OR-NOR, NAND-OR, NAND-NOR, NOR-AND, NOR-NAND.
• The eight non-degenerate forms
• AND-OR, OR-AND, NAND-NAND, NOR-NOR, NOR-OR, NAND-AND, OR-NAND, AND-NOR.
• AND-OR and NAND-NAND = sum of products.
• OR-AND and NOR-NOR = product of sums.
• NOR-OR, NAND-AND, OR-NAND, AND-NOR = ?

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 Tabular Summary and Examples

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 F = BC’D’ + ACD’ + A’B’CD’
d = A’B’C’ +A’C’D + AB’C’D’

FIND
Sum of Minterms
Product of Maxterms
SOP
POS
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All NAND 35
All NOR
 Quiz No. 1
1. The state of a 12 bit register is 100010010111. What is its
contents if it represents
decimal digits in BCD
decimal digits in excess 3 code
decimal digits in 8, 4, -2, -1 code
a binary number
2. Perform subtraction (4)10 – (62)8 using both 2’s complement and
1’s complement.

3. Convert 5639 to Gray code. Modify the answer by adding even

parity to the result.

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