Chapter 8: Main Memory

Operating System Concepts – 9th Edition Silberschatz, Galvin and Gagne ©2013
 Background

 Program must be brought (from disk) into memory and

placed within a process for it to be run
 Main memory and registers are only storage CPU can
access directly
 Memory unit only sees a stream of addresses + read
requests, or address + data and write requests
 Register access in one CPU clock (or less)
 Main memory can take many cycles, causing a stall (not
enough memory available)
 Cache sits between main memory and CPU registers
 Protection of memory required to ensure correct operation

Operating System Concepts – 9th Edition 8.2 Silberschatz, Galvin and Gagne ©2013
 Base and Limit Registers
 A pair of base and limit registers define the logical address space
 CPU must check every memory access generated in user mode to
be sure it is between base and limit for that user

Operating System Concepts – 9th Edition 8.3 Silberschatz, Galvin and Gagne ©2013
 Hardware Address Protection

Operating System Concepts – 9th Edition 8.4 Silberschatz, Galvin and Gagne ©2013
 Logical vs. Physical Address Space

 The concept of a logical address space that is bound to a

separate physical address space is central to proper memory
management
 Logical address – generated by the CPU; also referred to
as virtual address
 Physical address – address seen by the memory unit
 Logical address space is the set of all logical addresses
generated by a program
 Physical address space is the set of all physical addresses
generated by a program

Operating System Concepts – 9th Edition 8.5 Silberschatz, Galvin and Gagne ©2013
 Memory-Management Unit (MMU)
 Hardware device that at run time maps virtual to physical
address
 Many methods possible, covered in the rest of this chapter
 To start, consider simple scheme where the value in the
relocation register is added to every address generated by a
user process at the time it is sent to memory
 The user program deals with logical addresses; it never sees the
real physical addresses
 Execution-time binding occurs when reference is made to
location in memory
 Logical address bound to physical addresses

Operating System Concepts – 9th Edition 8.6 Silberschatz, Galvin and Gagne ©2013
 Contiguous Allocation
 Main memory must support both OS and user processes
 Limited resource, must allocate efficiently
 Contiguous allocation is one early method
 Main memory usually into two partitions:
 Resident operating system, usually held in low memory with
interrupt vector
 User processes then held in high memory
 Each process contained in single contiguous section of
memory

Operating System Concepts – 9th Edition 8.7 Silberschatz, Galvin and Gagne ©2013
 Hardware Support for Relocation and Limit Registers

Operating System Concepts – 9th Edition 8.8 Silberschatz, Galvin and Gagne ©2013
 Fragmentation
 External Fragmentation – total memory space exists to
satisfy a request, but it is not contiguous
 Internal Fragmentation – allocated memory may be slightly
larger than requested memory; this size difference is memory
internal to a partition, but not being used
 First fit analysis reveals that given N blocks allocated, 0.5 N
blocks lost to fragmentation

Operating System Concepts – 9th Edition 8.9 Silberschatz, Galvin and Gagne ©2013
 Segmentation
 Memory-management scheme that supports user view of memory
 A program is a collection of segments
 A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays

Operating System Concepts – 9th Edition 8.10 Silberschatz, Galvin and Gagne ©2013
 User’s View of a Program

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 Logical View of Segmentation

4
1

3 2
4

user space physical memory space

Operating System Concepts – 9th Edition 8.12 Silberschatz, Galvin and Gagne ©2013
 Segmentation Architecture
 Logical address consists of a two tuple:
<segment-number, offset>,
The offset d of the logical address must be between 0 and the
segment limit
 Avoids internal fragmentation

 Segment table – maps two-dimensional physical addresses; each

table entry has:
 base – contains the starting physical address where the segments
reside in memory
 limit – specifies the length of the segment

 Segment-table base register (STBR) points to the segment table’s

location in memory

 Segment-table length register (STLR) indicates number of segments

used by a program;
segment number s is legal if s < STLR

Operating System Concepts – 9th Edition 8.13 Silberschatz, Galvin and Gagne ©2013
 Segmentation Architecture (Cont.)
 Protection
 With each entry in segment table associate:
 validation bit = 0  illegal segment
 read/write/execute privileges
 Protection bits associated with segments
 A segmentation example is shown in the following diagram

Operating System Concepts – 9th Edition 8.14 Silberschatz, Galvin and Gagne ©2013
 Segmentation Hardware

Operating System Concepts – 9th Edition 8.15 Silberschatz, Galvin and Gagne ©2013
 Paging
 Physical address space of a process can be noncontiguous;
process is allocated physical memory whenever the latter is
available
 Avoids external fragmentation
 Avoids problem of varying sized memory chunks

 Divide physical memory into fixed-sized blocks called frames

 Size is power of 2, between 512 bytes and 16 Mbytes
 Divide logical memory into blocks of same size called pages
 Keep track of all free frames
 To run a program of size N pages, need to find N free frames and
load program
 Set up a page table to translate logical to physical addresses
 Every process has its own page table

Operating System Concepts – 9th Edition 8.16 Silberschatz, Galvin and Gagne ©2013
 Address Translation Scheme
 Address generated by CPU is divided into:
 Page number (p) – used as an index into a page table which
contains base address of each page in physical memory
 Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit

page number page offset

p d
m -n n

 logical address (m) = total no of bits required to represent total

no of pages + bits required to map page offset
 For given logical address space 2m and page size 2n

Operating System Concepts – 9th Edition 8.17 Silberschatz, Galvin and Gagne ©2013
 Paging Hardware

Operating System Concepts – 9th Edition 8.18 Silberschatz, Galvin and Gagne ©2013
 Paging Model of Logical and Physical Memory

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 Paging Example

n=2 and m=4 32-byte memory and 4-byte pages

Operating System Concepts – 9th Edition 8.20 Silberschatz, Galvin and Gagne ©2013
 Paging (Cont.)
 Calculating internal fragmentation
 Page size = 2,048 bytes
 Process size = 72,766 bytes
 35 pages + 1,086 bytes
 Internal fragmentation of 2,048 - 1,086 = 962 bytes
 Worst case fragmentation = 1 frame – 1 byte
 On average fragmentation = 1 / 2 frame size
 So small frame sizes desirable?
 But each page table entry takes memory to track

Operating System Concepts – 9th Edition 8.21 Silberschatz, Galvin and Gagne ©2013
 Free Frames

Before allocation After allocation

Operating System Concepts – 9th Edition 8.22 Silberschatz, Galvin and Gagne ©2013
 Implementation of Page Table
 Page table is kept in main memory
 Page-table base register (PTBR) points to the page table
 Page-table length register (PTLR) indicates size of the page
table
 In this scheme every data/instruction access requires two
memory accesses
 One for the page table and one for the data / instruction
i.e. access to the corresponding frame
 The two memory access problem can be solved by the use of
a special fast-lookup hardware cache called associative
memory or translation look-aside buffers (TLBs)
 TLBs typically small (64 to 1,024 entries)
 On a TLB miss, value is loaded into the TLB for faster access
next time

Operating System Concepts – 9th Edition 8.23 Silberschatz, Galvin and Gagne ©2013
 Paging Hardware With TLB

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 Paging (Cont.)

Operating System Concepts – 9th Edition 8.25 Silberschatz, Galvin and Gagne ©2013
 Effective Access Time
 Associative memory Lookup =  time unit
 Can be < 10% of memory access time
 Hit ratio = 
 Hit ratio – percentage of times that a page number is found in the
associative registers; ratio related to number of associative
registers
 Consider  = 80%,  = 20ns for TLB search, 100ns for memory access
 Effective Access Time (EAT)
EAT = (TLB search + memory access time) * hit ratio +
(TLB search + 2* memory access time ) * miss ratio
Consider  = 80%,  = 20ns for TLB search, 100ns for memory access
 EAT = (20+100) * 0.8 + (20+200) * 0.2 = 140 ns
 Consider more realistic hit ratio ->  = 99%,  = 20ns for TLB search,
100ns for memory access
 EAT = (20+100) * 0.99 + (20+200) * 0.01 = 121ns

Operating System Concepts – 9th Edition 8.26 Silberschatz, Galvin and Gagne ©2013
 Memory Protection
 Memory protection implemented by associating protection bit
with each frame to indicate if read-only or read-write access is
allowed
 Can also add more bits to indicate page execute-only, and
so on
 Valid-invalid bit attached to each entry in the page table:
 “valid” indicates that the associated page is in the process’
logical address space, and is thus a legal page
 “invalid” indicates that the page is not in the process’ logical
address space
 Or use page-table length register (PTLR)
 Any violations result in a trap to the kernel

Operating System Concepts – 9th Edition 8.27 Silberschatz, Galvin and Gagne ©2013
 Valid (v) or Invalid (i) Bit In A Page Table

Operating System Concepts – 9th Edition 8.28 Silberschatz, Galvin and Gagne ©2013
 Structure of the Page Table
 Memory structures for paging can get huge using straight-
forward methods
 Consider a 32-bit logical address space as on modern
computers
 Page size of 4 KB (212)
 Page table would have 1 million entries (232 / 212)
 If each entry is 4 bytes -> 4 MB of physical address space /
memory for page table alone
 That amount of memory used to cost a lot
 Don’t want to allocate that contiguously in main memory
 Hierarchical Paging
 Hashed Page Tables
 Inverted Page Tables

Operating System Concepts – 9th Edition 8.29 Silberschatz, Galvin and Gagne ©2013
 Logical to Physical Address Translation in IA-32

Operating System Concepts – 9th Edition 8.30 Silberschatz, Galvin and Gagne ©2013
 Combined Segmentation and Paging
 To combine their advantages, some OSs page the segments (which could be
as large as 64K) to minimize external fragmentation.
 Several combinations exist – assume each process has:
 one segment table.
 several page tables: one page table per segment.
 The virtual address consists of:
 a segment number: used to index the segment table who’s entry gives
the starting address of the page table for that segment.
 a page number: used to index that page table to obtain the corresponding
frame number.
 an offset: used to locate the word within the frame.

Operating System Concepts – 9th Edition 8.31 Silberschatz, Galvin and Gagne ©2013
 Simple Combined Segmentation and Paging

 The Segment Base is the physical address of the page table of that
segment.
 Present/modified bits are present only in page table entry.
 Protection and sharing info most naturally resides in segment table entry.
 Ex: a read-only/read-write bit, a kernel/user bit...

Operating System Concepts – 9th Edition 8.32 Silberschatz, Galvin and Gagne ©2013
 Address Translation in combined Segmentation/Paging

Operating System Concepts – 9th Edition 8.33 Silberschatz, Galvin and Gagne ©2013
 End of Chapter 8

Operating System Concepts – 9th Edition Silberschatz, Galvin and Gagne ©2013