Computer Organization & Architecture

BEET-404

Unit 4
Memory Organization

Mr. Gaurav Kumar

Asst. Professor

Department of Computer Science & Engineering

Faculty Name: Subject Name:
Unit 4: Content
1. RAM & ROM Chips
2. Cache Organization

Faculty Name: Subject Name:

 RAM CHIP

•RAM is the main memory.

•A 128 * 8 RAM chip has a memory capacity of 128 words of eight bits (one byte) per word.
•This requires a 7-bit address and an 8-bit bidirectional data bus.
•The 8-bit bidirectional data bus allows the transfer of data either from memory to CPU during a read operation
or from CPU to memory during a write operation.
•The read and write inputs specify the memory operation, and the two chip select (CS) control inputs are for
enabling the chip only when the microprocessor selects it.
•The bidirectional data bus is constructed using three-state buffers.
•The output generated by three-state buffers can be placed in one of the three possible states which include a
signal equivalent to logic 1, a signal equal to logic 0, or a high-impedance state.

Faculty Name: Subject Name:

 RAM CHIP

Faculty Name: Subject Name:

 Function Table of a 128 * 8 RAM chip.

Faculty Name: Subject Name:

 Contd…

•From the functional table, we can conclude that the unit is in operation only when CS1 = 1 and CS2 = 0.
•The bar on top of the second select variable indicates that this input is enabled when it is equal to 0.
•The logic 1 and 0 are standard digital signals whereas the high-impedance state behaves like an open
circuit, which means that the output does not carry a signal and has no logic significance.

Faculty Name: Subject Name:

 ROM CHIP

•A ROM chip has a similar organization as a RAM chip. However, a ROM can only perform read operation;
the data bus can only operate in an output mode.
•The 9-bit address lines in the ROM chip specify any one of the 512 bytes stored in it.
•The value for chip select 1 and chip select 2 must be 1 and 0 for the unit to operate. Otherwise, the data
bus is said to be in a high-impedance state.

Faculty Name: Subject Name:

 ROM CHIP

Faculty Name: Subject Name:

 Memory Address Map

•The addressing of memory can establish by means of a table that specifies the memory address
assigned to each chip.
• The table, called a memory address map, is a pictorial representation of assigned address space for
each chip in the system.
•To demonstrate with a particular example, assume that a computer system needs 512 bytes of RAM
and 512 bytes of ROM.
The component column specifies whether a RAM or a ROM chip used.
Moreover, The hexadecimal address column assigns a range of hexadecimal equivalent addresses for
each chip.

Faculty Name: Subject Name:

 Contd…
•The address bus lines listed in the third column.
•Although there 16 lines in the address bus, the table shows only 10 lines because the other 6 not used in this example
and assumed to be zero.
•The small x‟s under the address bus lines designate those lines that must connect to the address inputs in each chip.
• Moreover, The RAM chips have 128 bytes and need seven address lines. The ROM chip has 512 bytes and needs 9
address lines.
•The x‟s always assigned to the low-order bus lines: lines 1 through 7 for the RAM. And lines 1 through 9 for the ROM.
•It is now necessary to distinguish between four RAM chips by assigning to each a different address. For this particular
example, we choose bus lines 8 and 9 to represent four distinct binary combinations.
• Also, The table clearly shows that the nine low-order bus lines constitute a memory space for RAM equal to 2 9 = 512
bytes.
•The distinction between a RAM and ROM address done with another bus line. Here we choose line 10 for this purpose.
When line 10 0, the CPU selects a RAM, and when this line equal to 1, it selects the ROM.
Faculty Name: Subject Name:
 Contd…

Faculty Name: Subject Name:

 Memory Connection to CPU
•RAM and ROM chips are connected to a CPU through the data and address buses.

•The low-order lines in the address bus select the byte within the chips and other lines in the address bus select a
particular chip through its chip select inputs.

•This configuration gives a memory capacity of 512 bytes of RAM and 512 bytes of ROM. It implements the memory map
of Table 1. Each RAM receives the seven low-order bits of the address bus to select one of 128 possible bytes.

•The particular RAM chip selected is determined from lines 8 and 9 in the address bus. This is done through a 2 x 4
decoder whose outputs go to the CS1 inputs in each RAM chip.

•When address lines 8 and 9 are equal to 00, the first RAM chip is selected. When 01, the second RAM chip is selected,
and so on. The RD and WR outputs from the microprocessor are applied to the inputs of each RAM chip.

Faculty Name: Subject Name:

Contd…

•The selection between RAM and ROM is achieved through bus line 10. The RAMs are selected when the
bit in this line is 0, and the ROM when the bit is 1.

•The other chip select input in the ROM is connected to the RD control line for the ROM chip to be
enabled only during a read operation. Address bus lines 1 to 9 are applied to the input address of ROM
without going through the decoder.

•This assigns addresses 0 to 511 to RAM and 512 to 1023 to ROM. The data bus of the ROM has only an
output capability, whereas the data bus connected to the RAMs can transfer information in both directions
.

Faculty Name: Subject Name:

 Memory connection to CPU

Faculty Name: Subject Name:

 Cache Organization

•Cache memory is placed between the CPU and the main memory.
•The data or contents of the main memory that are used frequently by CPU are stored in the
cache memory so that the processor can easily access that data in a shorter time.
•Whenever the CPU needs to access memory, it first checks the cache memory.
• If the data is not found in cache memory, then the CPU moves into the main memory.

Faculty Name: Subject Name:

Contd…

The basic operation of a cache memory is as follows:

•When the CPU needs to access memory, the cache is examined. If the word is found in the cache, it is
read from the fast memory.
•If the word addressed by the CPU is not found in the cache, the main memory is accessed to read the
word.
•A block of words one just accessed is then transferred from main memory to cache memory. The
block size may vary from one word (the one just accessed) to about 16 words adjacent to the one just
accessed.
•The performance of the cache memory is frequently measured in terms of a quantity called hit ratio.
•When the CPU refers to memory and finds the word in cache, it is said to produce a hit.
•If the word is not found in the cache, it is in main memory and it counts as a miss.
•The ratio of the number of hits divided by the total CPU references to memory (hits plus misses) is the
hit ratio.

Faculty Name: Subject Name:

 Cache Mapping

There are three different types of mapping used for the purpose of cache memory which are as
follows:

1. Direct mapping
2. Associative mapping
3. Set-Associative mapping

Faculty Name: Subject Name:

 1. Direct Mapping

•The cache consists of normal high-speed random-access memory. Each location in the cache holds the
data, at a specific address in the cache.
• This address is given by the lower significant bits of the main memory address.
•This enables the block to be selected directly from the lower significant bit of the memory address.
•The remaining higher significant bits of the address are stored in the cache with the data to complete
the identification of the cached data.

Faculty Name: Subject Name:

 Contd..

Faculty Name: Subject Name:

 2. Set Associative Mapping

•In set associative mapping a cache is divided into a set of blocks.

• The number of blocks in a set is known as associativity or set size.
• Each block in each set has a stored tag.
•This tag together with index completely identify the block.
• Set associative mapping allows a limited number of blocks, with the same index and different
tags.

Faculty Name: Subject Name:

Contd..

Faculty Name: Subject Name:

 3. Fully associative mapping

•Fully Associative Mapping refers to a technique of cache mapping that allows mapping of the
main memory block to a freely available cache line.
• Fully associative cache would permit the storage of data in any cache block.
•There would be no forcing of every memory address into a single particular block.
•In case the data and information are fetched from memory, then they can be placed in an
unused block of a cache.

Faculty Name: Subject Name:

 Fully associative mapping

Faculty Name: Subject Name: