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    static timing analysis

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    manansakhiya3112

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    static timing analysis

    Uploaded by

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    Download as pptx, pdf, or txt
    5 views21 pages

    static timing analysis

    Uploaded by

    manansakhiya3112

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
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    What is Static timing Analysis?

    • What is static Timing Analysis (STA) ?

    It is a method to determine if a circuit meets timing constraints without simulation.

    • Why Static Timing Analysis ?

    • 100 % path coverage is possible because no design specific pattern is required (All paths are assumed critical)
    • Process variation across die can be modeled
    • constraints and reports are concise and easy to interpret

    CONFIDENTIAL© Copyright 2006 Wipro Technologi 1


    es
    Inputs & Outputs of STA
    • Inputs
    • Netlist (verilog) : The gate level circuit description.
    • Constraints (sdc/tcl) : The design related data
    • Net Delays
    • Parasitics (SPEF) : These are the parasitics of the design extracted
    from physical design tools.
    OR
    • SDF : Standard Delay Format file containing back-annotated delays.
    • Models (lib/db): The delay model of every cell in the library

    • Outputs
    • Reports : The timing paths report which can be used for debugging.

    CONFIDENTIAL© Copyright 2006 Wipro Technologi 2


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    Basic STA concepts
    • Fundamental timing questions of a system
    • Can design work at specified clock speed ?

    • STA tool calculates


    • Arrival time (min/Early, max/Late)
    • Required time(min/Early, max/Late)
    • Slack

    CONFIDENTIAL© Copyright 2006 Wipro Technologi 3


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    Timing Paths

    Timing Point

    INPUT
    OUTPUT
    D Q D Q
    FF1 FF2

    CLOCK

    Each path has a startpoint and an endpoint


    Timing path Startpoints
    - Input ports,
    - Clock pins of flip-flops
    Timing path Endpoints
    - Output ports,
    - all input pins of flip-flops except clock pins

    CONFIDENTIAL© Copyright 2006 Wipro Technologi 4


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    Types of paths (I)

    CONFIDENTIAL© Copyright 2006 Wipro Technologi 5


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    Setup time

    Setup time: the time required for the data to be stable before the clock edge

    D1 Q1 Combo logic D2 Q2
    FF1 FF2
    4.5ns
    0.4ns
    CLK

    CLK
    Launch Edge
    setup violation
    Capture Edge

    D2
    4.9

    setup time

    CLK
    0.3
    0 4.7 5

    CONFIDENTIAL© Copyright 2006 Wipro Technologi 6


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    Hold time

    Hold time: the time required for the data to remain stable after the clock edge

    D1 Q1 D2 Q2
    FF1 FF2
    CLK1 0.4ns
    0.3ns CLK2

    CLK1
    Launch Edge
    Capture Edge
    CQ
    D2=Q1
    0.4
    Hold violation

    hold time

    CLK2 0.2

    CONFIDENTIAL© Copyright 2006 Wipro Technologi


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    Setup and Hold time

    Setup time: the time required for the data to be stable before the clock edge
    Hold time: the time required for the data to remain stable after the clock edge

    D1 Q1 D2 Q2
    FF1 FF2

    CLK
    hold time

    CLK Launch Edge


    Capture Edge
    setup time

    CQ
    D2=Q1

    CQ
    Q2
    CONFIDENTIAL© Copyright 2006 Wipro Technologi 8
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    Setup and Hold time in STA

    Setup Requirement Hold Requirement

    Clk
    at FF2
    0 100

    Data
    at D pin
    of FF2
    Early Required Time Late Required Time

    Data should change only


    within this window

    Important!!
    In STA, Setup is checked at next edge and hold is checked at same edge
    CONFIDENTIAL© Copyright 2006 Wipro Technologi 9
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    Setup •Check
    Setup check

    D Q D Q
    FF1 FF2

    CALCULATION:
    Arrival time (max) = clock delay FF1 (max) +clock-to-Q delay FF1 (max) + comb. Delay( max)
    Required time = clock adjust + clock delay FF2 (min) - set up time FF2
    Slack = Required time - Arrival time (since we want data to arrive before it is required)
    clock adjust = clock period (since setup is analyzed at next edge)
    CONFIDENTIAL© Copyright 2006 Wipro Technologi 10
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    Hold check
    • Hold check
    • .

    D Q D Q
    FF1 FF2

    CALCULATION:
    Arrival time = clock delay FF1 (min) +clock-to-Q delay FF1 (min) + comb. Delay( min)
    Required time = clock adjust + clock delay FF2 (max) + hold time FF2
    Slack = Arrival time - Required time (since we want data to arrive after it is required)
    clock adjust = 0 (sinceCONFIDENTIAL©
    hold is analyzedCopyright
    at same 2006
    edge)Wipro Technologi 11
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    STA Problems
    Calculation of Maximum clock
    frequency
    • When no delay in the clock path
    Calculation of Maximum clock
    frequency
    • When delay is there in the clock path
    Calculation of Maximum clock
    frequency
    • When delay is there in the clock path
    Calculation of Maximum clock
    frequency
    • When delay is there in the clock path

    Maximum datapath delay = 2ns+11ns+2ns+9ns+2ns= 26ns

    Minimum Clockpath delay = 2ns+2ns+5ns = 9ns

    Minium clock period = 26ns-9ns+4ns = 21ns

    Maximum clock frequency = 1/21ns =47.5 MHz.


    Calculation of Maximum clock
    frequency
    Calculation of Maximum clock
    frequency
    How to correct violation
    Setup slack correction:
    • Reduce the amount of buffering in the path
    • Upsize the cell
    • Swap HVT into LVT cells
    • Clock skew

    Hold slack correction:


    • Adding delays in the datapath
    • Decreasing the size of certain cells in the datapath

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