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Module5_DCVSL_Dynamic logic

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Module5_DCVSL_Dynamic logic

Uploaded by

manansakhiya3112
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© © All Rights Reserved
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Differential Cascode Voltage Switch Logic

Dr. S. Umadevi
Associate Professor,
SENSE, VIT Chennai
Differential Cascode Voltage Switch Logic
• Seeks the performance of ratioed circuits without the
static power consumption
• It uses both true and complementary input signals
and computes both true and complementary outputs
using a pair of nMOS pull-down networks, as shown
in Figure
• Ratioed logic style that completely eliminates static
currents and provides rail-to-rail swing.
• Based on two concepts:
– differential logic
– positive feedback

CMOS Combinational Circuit Design 2


Differential Cascode Voltage Switch Logic
• For any given input pattern, one of the pulldown will be “ON”,
and the other will be “OFF”.

• The pulldown network that is “ON” will pull that output


“LOW”. This “LOW” output turns “ON” the PMOS transistor to
pull the opposite output “HIGH”.

• When the opposite output rises, the other PMOS transistor


turns “OFF”. So no static power dissipation occurs.

CMOS Combinational Circuit Design 3


Differential Cascode Voltage Switch Logic – Logic
Circuit

CMOS Combinational Circuit Design 4


Differential Cascode Voltage Switch Logic –
AND/NAND gate

CMOS Combinational Circuit Design 5


Differential Cascode Voltage Switch Logic –
XOR/XNOR gate

CMOS Combinational Circuit Design 6


Differential Cascode Voltage Switch Logic –
XOR/XNOR gate

CMOS Combinational Circuit Design 7


Examples
• Implement the following logic function using Differential
Cascode Voltage Switch Logic (DCVSL). Assume that the
complementary signal is readily available.

Please note that the signal should be implemented on the


left side, whereas its complement should be implemented
on the right side. Comment on the merits and the
demerits of the DCVSL logic.
Advantages and Disadvantages
Advantage:
• DCVSL has a potential speed advantage because all of the logic is
performed with NMOS transistors, thus reducing the input capacitance
• Unlike pseudo-NMOS, the feedback tends to turn “OFF” the PMOS, so the
output will eventually settle to a legal logic level.
• Good for XOR/XNOR logic.

Disadvantage:
• A small PMOS transistor is slow at pulling the complementary output
“HIGH”.
• Contention current (A component of static power dissipation that occurs
when all transistors in a circuit are “ON” at the same time) during the
switching period also increases power consumption.
• DCVSL is poorly switched to generate NAND and NOR logic.
Dynamic Circuits
Ratioed circuit:
• Reduces the input capacitance by replacing the PMOS transistors
connected to the inputs with a single resistive pullup
Drawback:
The drawbacks of ratioed circuits include
• Slow rising transitions
• Contention on the falling transitions
• Static power dissipation
• Non-zero VOL

• Dynamic circuit eliminating these drawbacks by using a clocked pull-up


transistor rather than a PMOS that is always ON
Thank You

CMOS Combinational Circuit Design 15

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