Chapter 7:

Random-Access Memory (RAM)

 Data Storage (Volatile)
Data input
 Locations (Address)
 Byte or Word

Address Memory unit

Read 16 x 8
Write

Data output
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 Random-Access Memory (RAM)
 Data Storage (Volatile)
m Data input
 Locations (Address)
 Byte or Word

k Address Memory unit

10 Address lines Read 2k x m
 1024 locations Write
=1K

m Data output
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 Memory Decoding
 Memory Cell Select

Input BC Output

Select Read/Write

Input S Q Output

R Q

Read/Write
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 Memory Decoding
 Memory Array Input Data
0
Address I1 BC BC BC BC
Lines
I0
1
2x4 BC BC BC BC
Decoder
2
Memory BC BC BC BC
Enable E
3
BC BC BC BC
Read/Write

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Output Data
Read-Only Memory (ROM)

k Address ROM
Memory 2k x m
Enable

m Data output

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Read-Only Memory (ROM)

Conventional Array Logic

Symbol Symbol

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 Read-Only Memory (ROM)
 8 x 4 ROM 3x8
Decoder
0
1
2
Address I2 3
Lines I1 4
I0 5
Memory 6
Enable E 7

Output Data
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 Read-Only Memory (ROM)
 8 x 4 ROM 3x8
Decoder

Address Data 0
0 0 0 0000 1
0 0 1 1101 2
A2 I2 3
0 1 0 0011
A1 I1 4
0 1 1 1000
A0 I0 5
1 0 0 1111
1 0 1 1001 6
1 E 7
1 1 0 0111
1 1 1 0000

D3 D2 D1 D0

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 Types of ROMs
 Mask Programmed ROM
● Programmed during manufacturing
 Programmable Read-Only Memory (PROM)
● Blow out fuses to produce ‘0’
 Erasable Programmable ROM (EPROM)
● Erase all data by Ultra Violet exposure
 Electrically Erasable PROM (EEPROM)
● Erase the required data using an electrical signal

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 Programmable Logic Device (PLD)
 Boolean Functions:
● Sums-of-Products
● AND-plane followed by OR-plane

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

I2
I1
I0

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 Programmable Logic Device (PLD)
 PROM
Fixed
Inputs Programmable Outputs
AND array
OR array
(Decoder)

 PAL
Inputs Programmable Fixed Outputs
AND array OR array

 PLA
Inputs Programmable Programmable Outputs
AND array OR array

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 Programmable Array Logic (PAL)
1 2 3 4 5 6 7 8 9 10
Example 1

w(A,B,C,D) = ∑(2,12,13) 2 F1 w
3
x(A,B,C,D) = ∑(7,8,9,10,11,12,13,14,15) A I1

y(A,B,C,D) = ∑(0,2,3,4,5,6,7,8,10,11,15) 4

z(A,B,C,D) = ∑(1,2,8,12,13) 5 F2 x
6

Simplify: B I2

7
w = ABC’ + A’B’CD’
8 F3 y
x = A + BCD 9

y = A’B + CD + B’D’ C I3

10
z = ABC’ + A’B’CD’ + AC’D’ + A’B’C’D
11 F4 z
= w + AC’D’ + A’B’C’D 12

D I4

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 Programmable Logic Array (PLA)

A I1
B I2
C I3

0
Example: 1

F1 = AB’ + AC + A’BC’ F1

F2
F2 = (AC + BC)’

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 Sequential Programmable Logic Device
 Basic Macrocell Logic
CLK
OE

ENB
D Q

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 Homework
 Mano
● Chapter 7
♦ 7-1
♦ 7-2
♦ 7-3
♦ 7-18
♦ 7-19

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 Homework
7-1 The following memory units are specified by the number
of words times the number of bits per word. How many
address lines and input-output lines are needed in each
case? (a) 4K  16, (b) 2G  8, (c) 16M  32, (d) 256K 
64.
7-2 Give the number of bytes stored in the memories listed in
Problem 7-1.

7-3 Word number 723 in a memory of 1024  16 contains the

binary equivalent of 3,451. List the 10-bit address and the
16-bit memory content of the word.

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 Homework
7-18 Specify the size of a ROM (number of words and number
of bits per word) that will accommodate the truth table
for the following combinational circuit components:
(a) a binary multiplier that multiplies two 4-bit,
(b) a 4-bit adder-subtractor,
(c) a quadruple 2-to-1-line multiplexers with common
select and enable inputs, and
(d) a BCD-to-seven-segment decoder with an enable
input.

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 Homework
7-19 Tabulate the truth table for an 8  4 ROM that
implements the Boolean functions
A(x,y,z) = ∑(1,2,4,6)
B(x,y,z) = ∑(0,1,6,7)
C(x,y,z) = ∑(2,6)
D(x,y,z) = ∑(1,2,3,5,7)

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