Verilog Language

Concepts

Verilog Digital System Design 1

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 Module Basics

 Now we are going to see:

 How modules are developed

 How names, numbers and operators are used

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 Module Basics
Module
Basics

Code Logic Value

Format System

Wires and Module

Modules Names Numbers
Variables Ports

Verilog Verilog Array

Arrays
Operators Data Types Indexing

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 Code Format
Module
Basics

Code Logic Value

Format System

Wires and Module

Modules Names Numbers
Variables Ports

Verilog Verilog Array

Arrays
Operators Data Types Indexing

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 Code Format

 Verilog code is free format.

 Spaces and new lines are served as separators.
 It is case sensitive.
 Language keywords use lowercase characters.
 A comment designator start with // makes the rest of
line comment.
 The symbols /* … */ bracket the section of code
which is in between as a comment.

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 Logic Value System
Module
Basics

Code Logic Value

Format System

Wires and Module

Modules Names Numbers
Variables Ports

Verilog Verilog Array

Arrays
Operators Data Types Indexing

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 Logic Value System
 Bit type, or bits of vectors or arrays, of Verilog wires
and variables take the 4-value logic value system.

 Values in this system are 0, 1, Z and X.

 The values 0 and 1 logic low and high.

 The Z value represents an undriven, high impedance

value.

 The X value represent a conflict in multiple driving

values, an unknown or value of a variable not
initialized.

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 Logic Value System
0: 0
X 0

1: 1
x 1

X or x: 0 X 1
1 0
0
Z or z :
1 z
 Logic Values and Examples

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 Wires and Variables
Module
Basics

Code Logic Value

Format System

Wires and Module

Modules Names Numbers
Variables Ports

Verilog Verilog Array

Arrays
Operators Data Types Indexing

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 Wires and Variables

 Wires and Variables:

 net: represents a wire driven by a hardware

structure or output of a gate.

 reg: represents a variable that can be assigned

values in behavior description of a component in a

Verilog procedural block.

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 Modules
Module
Basics

Code Logic Value

Format System

Wires and Module

Modules Names Numbers
Variables Ports

Verilog Verilog Array

Arrays
Operators Data Types Indexing

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 Modules

 Module is the main structure of definition of

hardware components and testbenchs.
 Begins with module keyword and end with
endmodule.
 Immediately following the module keyword, port list
of the module appears enclosed in parenthesis.

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 Modules
`timescale 1ns/100ps
module FlipFlop (preset, reset, din, clk, qout);
input preset, reset, din, clk; Ports are only
output qout; listed in the port
reg qout; list and declared as
separate input and
always @ (posedge clk) begin output ports inside
if (reset) qout <= #7 0; the body of the
else if (preset) qout <= #7 1; .Flip-Flop module
else qout <= #8 din;
end
endmodule
 Separate Port Declarations Statements

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 Module Ports
Module
Basics

Code Logic Value

Format System

Wires and Module

Module
Modules Names Numbers
Variables Ports
Ports

Verilog Verilog Array

Arrays
Operators Data Types Indexing

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 Module Ports
 Inputs and outputs of a model must be declared as:
 input

 output

 inout

 By default, all declared ports are regarded as nets

and the default net type is used for the ports.
 Ports declared as output may be declared as reg.
This way they can be assigned values in
procedural blocks.
 An inout port can be used only as a net. Transfers
signal from and to module.

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 Names
Module
Basics

Code Logic Value

Format System

Wires and Module

Modules Names Numbers
Variables Ports

Verilog Verilog Array

Arrays
Operators Data Types Indexing

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 Names
 A stream of characters starting with a letter or an
underscore forms a Verilog identifier.
 The $ character and underscore are allowed in an
identifier.

 Verilog uses keywords that are all formed by streams

of lowercase characters.
 The names of system tasks and functions begin with
a $ character.
 Compiler directive names are preceded by the ` (back
single quote) character. Example: `timescale

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 Names
 The following are valid names for identifiers:

a_name , name1 , _name , Name,

Name$ , name55 , _55name , setup,
_$name.

 The following are Verilog keywords or system tasks.

$display, default, $setup,

begin

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 Numbers
Module
Basics

Code Logic Value

Format System

Wires and Module

Modules Names Numbers
Numbers
Variables Ports

Verilog Verilog Array

Arrays
Operators Data Types Indexing

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 Numbers
 Constants in Verilog are integer or real.
 Specification of integers can include X and Z in addition to
the standard 0 and 1 logic values.
 Integers may be
 Sized: Begins with the number of equivalent bits

 Unsized: Without the number of bits specification

 The general format for a sized integers is:

number_of_bits ‘ base_identifier digits
example: 6’b101100
The base specifier is a single lower or uppercase
character b, d, o or h
which respectively stand for binary, decimal, octal and
hexadecimal
bases.

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 Numbers
 Optionally, the base-identifier can be preceded by the
single character s (or S) to indicate a signed quantity.
 A plus or minus operator can be used on the left of the
number specification to change the sign of the
number.
 The underscore character (_) can be used anywhere in
a number for grouping its bits or digits for readability
purposes.

 Real constants in Verilog use the standard format as

described by IEEE std 754-1985, the IEEE standard for
double precision floating-point numbers. Examples:
1.9, 2.6E9, 0.1e-6, 315.96-12.

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 Arrays
Module
Basics

Code Logic Value

Format System

Wires and Module

Modules Names Numbers
Variables Ports

Verilog Verilog Array

Arrays
Operators Data Types Indexing

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 Arrays
 Verilog allows declaration and usage of
multidimensional arrays for nets or regs.
 Range specifications are enclosed in square brackets.
 The size and range specification of the elements of an
array come after the net type (e.g., wire) or reg
keyword.
 In the absence of a range specification before the
name of the array, an element size of one bit is
assumed.

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 Arrays
7 0
// An 8-bit vector Areg
reg [7:0] Areg;

Amem
// A memory of 8 one-bit elements
reg Amem [7:0];

0
 Array Structures

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 Arrays 7

// A two-dimensional memory of one-bit elements

reg Bmem [7:0] [0:3];
Bmem

7
0
// A memory of four 8-bit words
reg [7:0] Cmem [0:3]; Cmem

 Array Structures (Continued) 3

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 Arrays
// A two-dimensional memory of 3-bit elements
reg [2:0] Dmem [0:3] [0:4];

4
3
2
1
0
0
Dmem
3

 Array Structures

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 Verilog Operators
Module
Basics

Code Logic Value

Format System

Wires and Module

Modules Names Numbers
Variables Ports

Verilog
Verilog Verilog Array
Arrays
Operators
Operators Data Types Indexing

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Verilog Operators
Verilog
Operators

Basic Equality
Operators Operators

Boolean Shift
Operators Operators

Concatenation Conditional
Operators Operators

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 Basic Operators
Verilog
Operators

Basic Equality
Operators Operators

Boolean Shift
Operators Operators

Concatenation Conditional
Operators Operators

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 Basic Operators
 Arithmetic Operations in Verilog take bit, vector,
integer and real operands.
 Basic operators of Verilog are +, -, *, / and **.

 An X or a Z value in a bit of either of the operands of

a multiplication causes the entire result of the
multiply operation to become X.

 If any of the operands of a relational operator contain

an X or a Z, then the result becomes X.

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 Basic Operators
Example Results in
25 * 8’b6 150
25 + 8’b7 32
25 / 8’b6 4
22 % 7 1
8'b10110011 > 8’b0011 1
4’b1011 < 10 0
4’b1Z10 < 4’b1100 x
4’b1x10 < 4’b1100 x
4’b1x10 <= 4’b1x10 x
 Examples of Basic Operations

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Equality Operators
Verilog
Operators

Basic Equality
Operators Operators
Operators

Boolean Shift
Operators Operators

Concatenation Conditional
Operators Operators

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 Equality Operators
 Equality operators are categorized into two groups:
 Logical: Compare their operands for equality (==)

or inequality (!=)
Return a one-bit result, 0, 1, or Z

 An X ambiguity arises when an X or a Z occurs in one

of the operands.

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 Equality Operators

Example Results in
8’b10110011 == 8’b10110011 1
8’b1011 == 8’b00001011 1
4’b1100 == 4’b1Z10 0
4’b1100 != 8’b100X 1
8’b1011 !== 8’b00001011 0
8’b101X === 8’b101X 1

 Examples of Equality Operations

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Boolean Operators
Verilog
Operators

Basic Equality
Operators Operators

Boolean
Boolean Shift
Operators
Operators Operators

Concatenation Conditional
Operators Operators

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 Boolean Operators

 If an X or a Z appears in an operand of a logical

operator, an X will result.
 The complement operator ~ results in 1 and 0 for 0
and 1 inputs and X for X and Z inputs.

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 Shift Operators
Verilog
Operators

Basic Equality
Operators Operators

Boolean Shift
Operators Operators
Operators

Concatenation Conditional
Operators Operators

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 Shift Operators
 Logical shift operators (>> and << for shift right and
left) fill the vacated bit positions with zeros.

 Shift Operators

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Concatenation Operators
Verilog
Operators

Basic Equality
Operators Operators

Boolean Shift
Operators Operators

Concatenation Conditional
Operators Operators

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Concatenation Operators

 The notation used for this operator is a pair of curly

brackets ({...}) enclosing all scalars and vectors that
are being concatenated.

 If a is a 4-bit reg and aa is a 6-bit reg, the following

assignment places 1101 in a and 001001 in aa:
{a, aa} = 10’b1101001001

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Concatenation Operators
 If the a and aa registers have the values assigned to
them above, and aaa is a 16-bit reg data type, then
the assignment,
aaa = {aa, {2{a}}, 2’b11}
puts 001001_1101_1101_11 in aaa.

 {a, 2{b,c}, 3{d}} is equivalent to: {a, b, c, b, c, d, d,

d}

 {2’b00, 3{2’01}, 2’b11} results in: 10’b0001010111

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Conditional Operators
Verilog
Operators

Basic Equality
Operators Operators

Boolean Shift
Operators Operators

Concatenation Conditional
Operators Operators

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 Conditional Operators
 expression1 ? expression2 : expression3

If expression1 is true, then

expression2 is selected as
… the result of the operation;
assign a = (b == otherwise expression3 is
;c)? 1 : 0 .selected
…

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Verilog Data Types
Verilog
Data Types

Net Reg
Declarations Declarations

Signed
Parameters
Data

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Net Declarations
Verilog
Data Types

Net Reg
Declarations Declarations

Signed
Parameters
Data

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 Net Declarations
 This statement declares wires used between gates or
Boolean expressions representing logic structures.
wire w, n, m, p;

 By default, ports of a module are net of wire type.

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Reg Declarations
Verilog
Data Types

Net Reg
Reg
Declarations Declarations
Declarations

Signed
Parameters
Data

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 Reg Declarations

 reg is a variable for holding intermediate signal

values or nonhardware parameters and function
values.

 The reg declaration shown below declares a, b and ci

as reg types with 0 initial values.
reg a=0, b=0, ci=0;

 The default initial value of a declared reg is (X).

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 Signed Data
Verilog
Data Types

Net Reg
Declarations Declarations

Signed
Parameters
Data

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 Signed Data

 Verilog net and reg types can be declared as signed.

In below example areg is declared as a signed reg.
reg signed [15:0] areg;

 A signed reg that is shifted right by the >>> operator

is sign filled, whereas an unsigned reg shifted by this
operator is zero-filled.

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 Parameters
Verilog
Data Types

Net Reg
Declarations Declarations

Signed
Parameters
Parameters
Data

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 Parameters

 Parameters in Verilog do not belong to either the

variable or the net group. Parameters are constants
and cannot be changed at runtime. Parameters can
be declared as signed, real, integer, time or realtime.

Example Explanation
parameter p1=5, p2=6; 32 bit parameters
parameter [4:0] p1=5, p2=6; 5 bit parameters
parameter integer p1=5; 32 bit parameters
parameter signed [4:0] p1=5; 5 bit signed parameters

 Parameter Examples

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Verilog Simulation
Model
Verilog
Simulation
Model

Continuous Procedural
Assignments Assignments

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Continuous Assignments

Verilog
Simulation
Model

Continuous Procedural
Continuous
Assignments
Assignment Assignments

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Continuous Assignments
Continuous
Assignments

Simple Delay
Assignments Specification

Strength Net Declaration

Specification Assignments

Multiple
Drives

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Simple Assignments
Continuous
Assignments

Simple
Simple Delay
Assignments
Assignments Specification

Strength Net Declaration

Specification Assignments

Multiple
Drives

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 Simple Assignments

 A continuous assignment in Verilog is used only in

concurrent Verilog bodies.

 This assignment represents a net driven by a gate

output or a logic function.
assign w = m | p;

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Delay Specification
Continuous
Assignments

Simple Delay
Assignments Specification

Strength Net Declaration

Specification Assignments

Multiple
Drives

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 Delay Specification

 assign #2 w = m | p;

This assignment becomes active when m or p

changes. At this time, the new value of the m | p
expression is evaluated, and after a wait time of 2
time units, this new value is assigned to w.

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 Delay Specification

`timescale 1ns/100ps

module Mux2to1 (input a, b, c, output w);

wire n, m, p;
assign #3 m = a & b; Regardless of position
in the code, each
assign #3 p = n & c;
assignment waits for a
assign #6 n = ~b; right-hand-side variable
assign #2 w = m | p; to change for it to
endmodule .execute

 Concurrent Continuous Assignments

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 Delay Specification

 Simulation Run Showing a Glitch The simulation of the

previous circuit results in a
glitch due to a
hazard on w. The event-1
Verilog Digital System Design
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driven simulation
61 of
Strength Specification
Continuous
Assignments

Simple Delay
Assignments Specification

Strength Net Declaration

Specification Assignments

Multiple
Drives

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 Simple Assignments

 Net strengths are specified by a pair of strength

values bracketed by a set of parenthesis, as shown
below.
assign (strong0, strong1) w = m | p;

 One strength value is for logic 1 and one is for logic

0, and the order in which the strength values appear
in the set of parenthesis is not important.

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Net Declaration
Assignments
Continuous
Assignments

Simple Delay
Assignments Specification

Strength Net Declaration

Specification Assignments

Multiple
Drives

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 Net Declaration
Assignments
`timescale 1ns/100ps

module Mux2to1 (input a, b, c, output w);

wire #3
m = a & b,
p = n & c,
n = ~b,
w = m | p;
endmodule

 Using net_declaration_assignment

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Procedural Assignments

Verilog
Simulation
Model

Continuous Procedural
Procedural
Assignment Assignments
Assignment

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 Procedural Assignments

 Procedural assignments in Verilog take place in the

initial and always procedural constructs, which are
regarded as procedural bodies.

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 Procedural Flow Control

 Statements in a procedural body are executed when

program flow reaches them.

 Flow control statements are classified as delay

control and event control.

 An event or delay control statement in a procedural

body causes program flow to be put on hold
temporarily.

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 Procedural Blocking
Assignments
 A blocking assignment uses a reg data type on the
left-hand side and an expression on the right-hand
side of an equal sign.

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 Procedural Blocking
Assignments
initial begin : Blocking_Assignment_to_b
b = 1;
#100
b = #80 0; b = #120 1;
#100
$display ("Initial Block with Blocking Assignment
to b Ends at:", $time);
end The $display
statement
displays 400
 Blocking Procedural Assignments

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 Procedural Non-blocking
Assignments
 A non-blocking assignment uses the left arrow
notation <= (left angular bracket followed by the
equal sign) instead of the equal sign used in blocking
assignments.

 When flow reaches a non-blocking assignment, the

right-hand side of the assignment is evaluated and
will be scheduled for the left-hand side reg to take
place when the intra-assignment control is satisfied.

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 Procedural Non-blocking
Assignments
initial begin : Non_blocking_Assignment_to_a
a = 1;
#100
a <= #80 0; a <= #120 1;
#100
$display ("Initial Block with Non-blocking
Assignment to a Ends at:", $time);
end
The $display
statement
displays 200
 Non-blocking Procedural Assignments

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 Procedural Non-blocking
Assignments

 Comparing Blocking and Non-blocking Procedural Assignments

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