1_Introduction_to_verilog

_verilog

Uploaded by

shaik shareef

Available Formats

Download as PPTX, PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

18 views

1_Introduction_to_verilog

_verilog

Uploaded by

shaik shareef

Available Formats

Download as PPTX, PDF, TXT or read online on Scribd

You are on page 1/ 15

About the course

instructor…..

Bijjula pruthwiraj
M.Tech(NIT-DELHI)
[email protected]
Introduction to
VERILOG
Agenda:

• Why HDL’s & Evolution of HDL’s

• Typical design flow
• Importance of HDL’s
• Why Verilog HDL
• Trends in Verilog
• Basic Methodologies
• Modules and Instances
Why HDL’s ? & Evolution of HDL’s

Tech Evolution:
• SSI (Small Scale Integration)
• MSI (Medium Scale Integration)
• LSI (Large Scare Integration)
• VLSI (Very Large Scale Integration)

Software languages:
• FORTRAN, Pascal, and C
Importance of HDL’s

• Traditional schematic-based design is difficult

• No worry of fabrication technology (front end)
• Functional verification is easy, prevent bug early
• Gate-level schematics are almost incomprehensible for very
complex designs.
Why Verilog HDL

• Easy to learn, easy to use, and C-type syntax

• Different Levels of abstractions (switch, gates, RTL and
behavioral)
• Most synthesis tool supports
• libraries for post logic synthesis
• The Programming Language Interface (PLI)
Trends in Verilog

• HDL at an RTL
• Verilog Keeps on updates (Verilog-95, 2001,
2005,2009)
• Supports verification methodologies
• Assertion checking techniques
• Support for automatic stimulus creation (test bench)
Basic Methodologies
• Top-down method

• Bottom-up method
Typical design flow
Modules :

Modules:

module <module_name> (<module_terminal_list>);

...
<module internals>
...
...
endmodule

<module internals>
a. data flow
b. behavioral
c. structural
d. Mixed modeling
e. Gate level
f. Switch level
Component of simulation
Assignments
1. What are other HDL’s than Verilog HDL?
2. How hardware design was done before Verilog HDL ?
… ?
ns
sti o
ue
Q

Hardware Description Language Demystified: Explore Digital System Design Using Verilog HDL and VLSI Design Tools
From Everand
Hardware Description Language Demystified: Explore Digital System Design Using Verilog HDL and VLSI Design Tools
Rajkumar Sarma
No ratings yet
HDL Design Lec1 1613730817095
No ratings yet
HDL Design Lec1 1613730817095
10 pages
Verilog
No ratings yet
Verilog
29 pages
Verilog
No ratings yet
Verilog
13 pages
18EC56 Verilog HDL Introduction
No ratings yet
18EC56 Verilog HDL Introduction
19 pages
unit 1 DDTV
No ratings yet
unit 1 DDTV
114 pages
Unit 1 - LP1
No ratings yet
Unit 1 - LP1
59 pages
18EC56 Verilog HDL Module 1 2020
No ratings yet
18EC56 Verilog HDL Module 1 2020
52 pages
DDTV Unit 1
No ratings yet
DDTV Unit 1
131 pages
Lesson 1.1 Introduction To HDL
No ratings yet
Lesson 1.1 Introduction To HDL
23 pages
Digital Design Concepts, Introduction To Verilog
No ratings yet
Digital Design Concepts, Introduction To Verilog
52 pages
Verilog Course
No ratings yet
Verilog Course
181 pages
DSD Module 2
No ratings yet
DSD Module 2
118 pages
Verilog HDL Syllabus
No ratings yet
Verilog HDL Syllabus
28 pages
Seminar On HDL's and HVL's
No ratings yet
Seminar On HDL's and HVL's
25 pages
CH 01
No ratings yet
CH 01
14 pages
Verilog Tutorial
No ratings yet
Verilog Tutorial
19 pages
HDL Programming Lab Manual Final Updated
No ratings yet
HDL Programming Lab Manual Final Updated
77 pages
Module 1
No ratings yet
Module 1
12 pages
Chapter-3 verilogHDLUPD
No ratings yet
Chapter-3 verilogHDLUPD
138 pages
Digital Ic Design Skill Lab
No ratings yet
Digital Ic Design Skill Lab
33 pages
Ch-2 Hardware Descriptive Lanquage_1
No ratings yet
Ch-2 Hardware Descriptive Lanquage_1
50 pages
Verilog HDL: A Guide To Digital Design DS TH I and Synthesis
No ratings yet
Verilog HDL: A Guide To Digital Design DS TH I and Synthesis
62 pages
Digital Designing in Verilog HDL
No ratings yet
Digital Designing in Verilog HDL
46 pages
Verilog HDL A Guide To Digital Design and Synthesis Samir Palnitkar Sunsoft Press 1996
No ratings yet
Verilog HDL A Guide To Digital Design and Synthesis Samir Palnitkar Sunsoft Press 1996
3 pages
18EC56 Verilog HDL Module 1 2020
No ratings yet
18EC56 Verilog HDL Module 1 2020
52 pages
02 DSD Presentation
No ratings yet
02 DSD Presentation
39 pages
Introduction To HDL
No ratings yet
Introduction To HDL
28 pages
Hardware Description Language
No ratings yet
Hardware Description Language
23 pages
3ST Verilog STWT Slides
No ratings yet
3ST Verilog STWT Slides
172 pages
Verilog HDL - Text Book
No ratings yet
Verilog HDL - Text Book
158 pages
2012 SysVerilog For FPGAs Paper
No ratings yet
2012 SysVerilog For FPGAs Paper
18 pages
Verilog Chapter1 Introduction
No ratings yet
Verilog Chapter1 Introduction
33 pages
Verilog HDL
No ratings yet
Verilog HDL
193 pages
Module 4A HDL Intro 04-12-23
No ratings yet
Module 4A HDL Intro 04-12-23
15 pages
Verilog Part1
No ratings yet
Verilog Part1
77 pages
L02 - Introduction To Verilog
No ratings yet
L02 - Introduction To Verilog
17 pages
L02 - Introduction To Verilog
No ratings yet
L02 - Introduction To Verilog
17 pages
1345554882
No ratings yet
1345554882
15 pages
Verilog
No ratings yet
Verilog
4 pages
FALLSEM2023-24 BEEE206L TH VL2023240102927 2023-08-05 Reference-Material-I
No ratings yet
FALLSEM2023-24 BEEE206L TH VL2023240102927 2023-08-05 Reference-Material-I
9 pages
" Verilog: Indra Reddy
No ratings yet
" Verilog: Indra Reddy
167 pages
Verilog HDL - Mod - 1
No ratings yet
Verilog HDL - Mod - 1
27 pages
Ece5440 Chapter1 VerilogIntroduction Updated
No ratings yet
Ece5440 Chapter1 VerilogIntroduction Updated
12 pages
Digital Design and Synthesis: Instructors
No ratings yet
Digital Design and Synthesis: Instructors
11 pages
Systemverilog vs Verilog
No ratings yet
Systemverilog vs Verilog
12 pages
Digital Design Using Verilog HDL: Fall 21
No ratings yet
Digital Design Using Verilog HDL: Fall 21
39 pages
Prelim Module1 - B
100% (1)
Prelim Module1 - B
11 pages
Unit 1
No ratings yet
Unit 1
299 pages
Introduction To Verilog
No ratings yet
Introduction To Verilog
22 pages
Unit I 3rd Part
No ratings yet
Unit I 3rd Part
63 pages
DSDV Lab @vtudeveloper.in
No ratings yet
DSDV Lab @vtudeveloper.in
49 pages
DDCO LAB Manual (1.1)
No ratings yet
DDCO LAB Manual (1.1)
54 pages
Introduction To Verilog
No ratings yet
Introduction To Verilog
142 pages
FALLSEM2021-22 ECE5017 ETH VL2021220105371 2021-09-23 Bobk
No ratings yet
FALLSEM2021-22 ECE5017 ETH VL2021220105371 2021-09-23 Bobk
403 pages
Verilog HDL - Samir Palnitkar PDF
No ratings yet
Verilog HDL - Samir Palnitkar PDF
403 pages
Verilog HDL - Samir Palnitkar
No ratings yet
Verilog HDL - Samir Palnitkar
403 pages
Verilog HDL - Samir Palnitkar
No ratings yet
Verilog HDL - Samir Palnitkar
403 pages
Blockchain Foundation Courseware - English
From Everand
Blockchain Foundation Courseware - English
Eppo Luppes
No ratings yet
C++ Debugging from Scratch: A Practical Guide with Examples
From Everand
C++ Debugging from Scratch: A Practical Guide with Examples
William E. Clark
No ratings yet
associtaive array
No ratings yet
associtaive array
7 pages
SV PPT
100% (1)
SV PPT
26 pages
verilog question 2
No ratings yet
verilog question 2
27 pages
SystemVerilog Topics PPT [Autosaved]
No ratings yet
SystemVerilog Topics PPT [Autosaved]
103 pages
time scale
No ratings yet
time scale
1 page
Assertion basics and problems by jai
No ratings yet
Assertion basics and problems by jai
36 pages

1_Introduction_to_verilog

Uploaded by

1_Introduction_to_verilog

Uploaded by

About the course

• Why HDL’s & Evolution of HDL’s

• Traditional schematic-based design is difficult

• Easy to learn, easy to use, and C-type syntax

module <module_name> (<module_terminal_list>);

You might also like