+

A Top-Level View of Computer

Function and Interconnection
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Computer Components
 Contemporary computer designs are based on concepts
developed by John von Neumann at the Institute for
Advanced Studies, Princeton
 Referred to as the von Neumann architecture and is
based on three key concepts:
 Data and instructions are stored in a single read-write
memory
 The contents of this memory are addressable by location,
without regard to the type of data contained there
 Execution occurs in a sequential fashion (unless explicitly
modified) from one instruction to the next

 Hardwired program
 The result of the process of connecting the various
components in the desired configuration
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Hardware
and Software
Approaches

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 Software
• A sequence of codes or instructions
• Part of the hardware interprets each Software
instruction and generates control signals
• Provide a new sequence of codes for each new
program instead of rewiring the hardware
Major components:
• CPU I/O
• Instruction interpreter
Components
• Module of general-purpose arithmetic and
logic functions
• I/O Components
• Input module
+ • Contains basic components for accepting
data and instructions and converting them
into an internal form of signals usable by
the system
• Output module
• Means of reporting results
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+
Fetch Cycle
 At the beginning of each instruction cycle the
processor fetches an instruction from memory
 The program counter (PC) holds the address of the
instruction to be fetched next
 The processor increments the PC after each
instruction fetch so that it will fetch the next
instruction in sequence
 The fetched instruction is loaded into the instruction
register (IR)
 The processor interprets the instruction and performs
the required action

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 Action Categories
• Data transferred • Data transferred to
from processor to or from a peripheral
memory or from device by
memory to transferring
processor between the
processor and an
I/O module

Processor Processor
-memory -I/O

Data
Control processin
g
• An instruction may • The processor may
specify that the perform some
sequence of arithmetic or logic
execution be operation on data
altered

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 Memory Memory buffer
address register (MBR) MEMORY
register (MAR) • Contains the data
• Specifies the to be written into
address in memory or
memory for the receives the data
next read or write read from
memory

MAR
I/O address I/O buffer
register register
(I/OAR) (I/OBR)
• Specifies a • Used for the
+ particular I/O exchange of data
device between an I/O
module and the
CPU MBR

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+

 Memory address registers(MAR) : It is connected to

the address lines of the system bus. It specifies the
address in memory for a read or write operation.
 Memory Buffer Register(MBR) : It is connected to
the data lines of the system bus. It contains the value
to be stored in memory or the last value read from the
memory.
 Program Counter(PC) : Holds the address of the next
instruction to be fetched.
 Instruction Register(IR) : Holds the last instruction
fetched.

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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+  Fetch: In the fetch cycle, the CPU retrieves the instruction from
memory. The instruction is typically stored at the address specified by
the program counter (PC). The PC is then incremented to point to the
next instruction in memory.

 Decode: In the decode cycle, the CPU interprets the instruction and
determines what operation needs to be performed. This involves
identifying the opcode and any operands that are needed to execute
the instruction.

 Execute: In the execute cycle, the CPU performs the operation

specified by the instruction. This may involve reading or writing data
from or to memory, performing arithmetic or logic operations on data,
or manipulating the control flow of the program.

 There are also some additional steps that may be performed during
the instruction cycle, depending on the CPU architecture and
instruction set:

 Fetch operands: In some CPUs, the operands needed for an

instruction are fetched during a separate cycle before the execute
cycle. This is called the fetch operands cycle.

 Store results: In some CPUs, the results of an instruction are stored

during
© 2016 Pearson a separate
Education, Inc., Hoboken, cycle after
NJ. All rights the execute cycle. This is called the
reserved.
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+
Interrupts

 An interrupt is a signal emitted by hardware or software

when a process or an event needs immediate attention. It
alerts the processor to a high-priority process requiring
interruption of the current working process. In I/O devices,
one of the bus control lines is dedicated for this purpose and
is called the Interrupt Service Routine (ISR).
 When a device raises an interrupt at the process, the
processor first completes the execution of an instruction.
Then it loads the Program Counter (PC) with the address
of the first instruction of the ISR. Before loading the program
counter with the address, the address of the interrupted
instruction is moved to a temporary location. Therefore,
after handling the interrupt, the processor can continue with
the process.

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+
A single computer can perform only one computer
instruction at a time. But, because it can be interrupted,
it can manage how programs or sets of instructions will
be performed. This is known as multitasking.

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+
Types of Interrupt

 An operating system usually has some code that is

called an interrupt handler. The interrupt handler
prioritizes the interrupts and saves them in a queue if
more than one is waiting to be handled. The operating
system has another little program called
a scheduler that figures out which program to control
next.

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 Table 3.1

Classes of Interrupts

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+
Interrupt Handling

 After every instruction cycle, the processor will check for interrupts to
be processed.
 If there is no interrupt in the system, it will go for the next instruction
cycle, given by the instruction register.
 If there is an interrupt present, then it will trigger the interrupt handler.
The handler will stop the present instruction that is processing and save
its configuration in a register and load the program counter of the
interrupt from a location given by the interrupt vector table.
 After processing the interrupt by the processor, the interrupt handler
will load the instruction and its configuration from the saved register.
The process will start its processing where it's left.
 This saves the old instruction processing configuration, and loading the
new interrupt configuration is also called context switching. There are
different types of interrupt handlers.
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Handling Multiple Devices
 When more than one device raises an interrupt request signal,
additional information is needed to decide which device to
consider first. The following methods are used to decide which
device to select first,

1. Polling
In polling, the first device encountered with the IRQ bit set is to
be serviced first, and appropriate ISR is called to service the
same. It is easy to implement, but a lot of time is wasted by
interrogating the IRQ bit of all devices.
+
Handling Multiple Devices

2. Vectored Interrupts
In vectored interrupts, a device requesting an interrupt identifies itself
directly by sending a special code to the processor over the bus. This
enables the processor to identify the device that generated the
interrupt. The special code can be the starting address of the ISR or
where the ISR is located in memory and is called the interrupt vector.

3. Interrupt Nesting
In this method, the I/O device is organized in a priority structure.
Therefore, an interrupt request from a higher priority device is
recognized, whereas a lower priority device is not. The processor
accepts interrupts only from devices/processes having priority more
than it.
Processors priority is encoded in a few bits of PS (Process Status
register), and it can be changed by program instructions that write into
the PS. The processor is in supervised mode only while executing OS
routines, and it switches to user mode before executing application
programs.
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+
Bus

 The electrically conducting path along which data is

transmitted inside any digital electronic device.
 A Computer bus consists of a set of parallel conductors,
which may be conventional wires, copper tracks on a
PRINTED CIRCUIT BOARD, or microscopic aluminium
trails on the surface of a silicon chip.
 Each wire carries just one bit, so the number of wires
determines the largest data WORD the bus can
transmit: a bus with eight wires can carry only 8- bit
data words, and hence defines the device as an 8-bit
device.

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+
Bus contd…

 The bus is a communication channel.

 The characteristic of the bus is shared transmission
media.
 The limitation of a bus is only one transmission at a
time.
 A bus which is used to provide communication between
the major components of a computer is called
a System bus.

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 A communication pathway Signals transmitted by
connecting two or more any one device are
devices available for reception by
• Key characteristic is that it is a
shared transmission medium
all other devices attached
to the bus
Bus
• If two devices transmit during
the same time period their
signals will overlap and
Inter
conn
become garbled

Typically consists of
multiple communication
Computer systems
contain a number of ecti
different buses that
lines
• Each line is capable of
transmitting signals
provide pathways
between components at
on
representing binary 1 and various levels of the
binary 0 computer system
hierarchy

System bus
• A bus that connects major The most common
computer components computer interconnection
(processor, memory, I/O) structures are based on
the use of one or more
system buses

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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
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 Data Bus
 Used to carry the binary data between the CPU, memory
and IO.
 Bidirectional.
 The number of lines is referred to as the width of the
data bus
 Based on the width of a data bus we can determine the
word length of a CPU.
 Based on the word length we can determine the
performance of a CPU.
 May consist of 32, 64, 128, or more separate lines
 The width of the data bus is a key factor in determining
overall system performance
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+ Address Bus

 Used to designate the source or destination of the data on the

data bus
 If the processor wishes to read a word of data from memory it
puts the address of the desired word on the address lines

 Width determines the maximum possible memory capacity of

the system

 Also used to address I/O ports

 The higher order bits are used to select a particular module on
the bus and the lower order bits select a memory location or
I/O port within the module

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 Address Bus

Data Bus

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 Control Bus

• Used to control the access and the use of the data

and address lines
• Because the data and address lines are shared by all
components there must be a means of controlling
their use
• Control signals transmit both command and timing
information among system modules
• Timing signals indicate the validity of data and
address information
• Command signals specify operations to be
performed

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+
I/O Function
 I/O module can exchange data directly with the processor
 Processor can read data from or write data to an I/O
module
 Processor identifies a specific device that is controlled by a
particular I/O module
 I/O instructions rather than memory referencing instructions

 In some cases it is desirable to allow I/O exchanges to

occur directly with memory
 The processor grants to an I/O module the authority to read
from or write to memory so that the I/O memory transfer can
occur without tying up the processor
 The I/O module issues read or write commands to memory
relieving the processor of responsibility for the exchange
 This operation is known as direct memory access (DMA)

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 The interconnection structure must support the
following types of transfers:

Memory
Processo I/O to I/O to or
to Processo
r to processo from
processo r to I/O
memory r memory
r
An I/O
module is
allowed to
exchange
data
Processor Processor directly
reads an Processor reads Processor with
instructio writes a data from sends memory
n or a unit unit of an I/O data to without
of data data to device via the I/O going
from memory an I/O device through
memory module the
processor
using
direct
memory
access

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+
Single bus structure

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+
Multi bus Structure

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+
Multiple bus hierarchies

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Multiple bus hierarchies
High speed Architecture

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+ Summary

 Computer components
 Computer function A Top-Level View of
 Instruction fetch and
execute Computer Function
 Interrupts and
 I/O function Interconnection
 Interconnection structures
 Bus interconnection

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