DIT 002 –

FUNDAMENTALS OF
INFORMATION
TECHNOLOGY
MOD 5 - Memory and Storage
Organization
Learning Objectives
• What is Memory?
• Memory Organization
• Memory Speed
• Classes of Memory
• Main Memory Design
• Cache Memory
• Direct mapping
• Cache mapping
• Set associative mapping

MOD 5 - Memory and Storage Organisation 2

The human brain starts working the moment you are
born and never stops until you stand up to speak in
public.

George Jessel
What is Memory?
• Memory is the electronic holding place for the instructions and data
a computer needs to reach quickly.
• It's where information is stored for immediate use.
• Computer memory stores information, such as data and programs, for
immediate use in the computer.
• The term memory is often synonymous with the terms RAM, main
memory, or primary storage.
• Archaic synonyms for main memory include core and store.

MOD 5 - Memory and Storage Organisation 4

 Memory Organization
• Memory organization is an important aspect of computer architecture, also
known as the organization of computer systems (COA).
• It refers to the way that the computer’s memory is arranged and managed.
• The memory of system can be thought of as a large number of addressable
storage locations.
• Each location can store a fixed amount of data, typically measured in bits or
bytes.
• The way these locations are organized and accessed can have a notable
impact on the overall production and functionality of the system.

MOD 5 - Memory and Storage Organisation 5

• Memory organization involves the use of different types of memory,
including:
i. RAM
ii. ROM
iii. Cache memory
iv. Virtual memory
v. Flash memory, and
vi. Magnetic disks
• Each type of memory is used for a specific purpose and has its own
advantages and disadvantages.

MOD 5 - Memory and Storage Organisation 6

• Memory organization is also important for the efficient management of
data and instructions within a computer system.
• It involves techniques such as memory allocation, virtual memory
management, and cache management.
• These techniques help to optimize the use of memory and improve
system performance.
• Overall, memory organization is a critical aspect of computer
architecture that plays a important role in determining the performance,
functionality, and efficiency of a computer system.

MOD 5 - Memory and Storage Organisation 7

Types Of Memory Organization :
• There are several types of memory organization used in computer
systems, each with its own advantages and disadvantages.
• Here are the most common types of memory organization:

MOD 5 - Memory and Storage Organisation 8

MOD 5 - Memory and Storage Organisation 9
 Memory Organization
• In a typical computer system, the storage system is organized
according to the following hierarchy:

slow access (1-5 s.) and large capacity (almost unlimited)

Archival Storage (magnetic tape

or photographic)
Moving head disk (magnetic or optical)

High speed drum

decreasing Charge Coupled Device decreasing

cost/bit access time
Main memory

Cache

Internal

fast access (1-20 ns.) and small capacity (1-4K byte)

i. Von Neumann architecture
• This type of memory organization is named after the computer
scientist John von Neumann, who first proposed the concept.
• In this architecture, in the same memory we can store both
instructions and data.
• This memory organization is simple and easy to implement, but it can
lead to bottlenecks as the system tries to access both instructions and
data at the same time.

MOD 5 - Memory and Storage Organisation 11

MOD 5 - Memory and Storage Organisation 12
ii. Harvard architecture
• In this type of memory organization, program instructions and data
are stored in separate memory spaces.
• This allows for parallel access to instructions and data, which can lead
to faster performance.
• However, the Harvard architecture is more complex to implement and
may require more hardware resources.

MOD 5 - Memory and Storage Organisation 13

MOD 5 - Memory and Storage Organisation 14
iii. Cache memory organization
• Small, fast memory that stores frequently used data and instructions.
• Cache memory is organized into levels, with each level providing
increasing storage capacity and decreasing speed.
• Cache memory organization is critical for improving system
performance, as it reduces the time it takes to access frequently used
data and instructions.

MOD 5 - Memory and Storage Organisation 15

MOD 5 - Memory and Storage Organisation 16
iv. Virtual memory organization
• It is a technique that allows a computer to use more memory than it
physically has.
• Virtual memory creates a virtual address space that is mapped to the
physical memory.
• This memory organization is critical for running large applications that
require more memory than is available on the system.

MOD 5 - Memory and Storage Organisation 17

MOD 5 - Memory and Storage Organisation 18
v. Flash memory organization
• It is a non-volatile memory that is used in portable devices, such as
USB drives and memory cards.
• Flash memory organization involves dividing the memory into blocks
and pages, with data stored in individual pages.
• This allows for efficient read and write operations and makes flash
memory ideal for storing data in portable devices.

MOD 5 - Memory and Storage Organisation 19

• The flash memory is spread across multiple flash chips, where each chip contains one or more flash dies, which are
individual pieces of silicon wafer that are connected together to the pins of the chip. ... ... an operation can be started in a
MOD 5 - Memory and Storage Organisation 20
different plane in the same die in a pipelined manner, every cycle
 Memory speed

• Access time (Ta)

• the average time taken to read a unit of information
e.g., 100 ns (100 x 10**-9 s)
• Access rate (Ra) = 1/Ta (bits/second)
e.g., 1/100ns = 10 Mb/s
• Cycle time (Tc)
• the average time lapse between two successive read
operations
e.g., 500 ns (500 x 10**-9 s)
• Bandwidth or transfer rate (Rc) = 1/Tc (bits/second)
e.g., 1/500ns = 2 Mb/s
 Classes of Memory
• RAM (“normal memory”)
• Direct-access storage: HD, CD ROM, DVD
• Sequential access storage tapes: DAT
• Associative (content-addressable) memory: searches
for data via bit patterns
• CAM (Content Addressable Memory)
• Includes comparison logic with each bit of storage.
• A data value is broadcast to all words of storage and compared with
the values there.
• Words which match are flagged.
• Subsequent operations can then work on flagged words.
• (computing-dictionary.thefreedictionary.com)
• ROM
 Categories of RAM and ROM

primary memory

RAM ROM

magnetic semiconductor Bipolar MOS

core
static dynamic Mask PROM
ROM Mask PROM EPROM,
ROM EAROM
 Main Memory Design

10
A9-A0
1K x 4 4
WE RAM chip D3-D0
CS

CS WE MODE Status of the Power

Bi-directional
Datelines D3-D0

H X not selected High impedance Standby

L L Write Acts as input bus Active

L H Read Acts as output bus Active

 Main Memory Design

Q. How do we build a 4K x 4 RAM using four 1K

x 4 RAM chips?

Chip A11 A10 A9 A8 A7 . . . A0 Range

0 0 0 x x x ... x 0000 to 1023
1 0 1 x x x ... x 1024 to 2047
2 1 0 x x x ... x 2048 to 3071
3 1 1 x x x ... x 3072 to 4096
 Main Memory Design
• Q. How do we build a 256KB RAM system with
an 16-bit address bus and four 64KB RAM chips?

• Memory band-switching

log2 n 1-of-n
Processor Decoder n
1 2 Enable n
Enable 2
Addr bus Enable 1
Memory bank
(On bus in parallel )
 Main memory design

• Memory address extension

Data bus 4-bit

base
Processor address Base
20 bit
Physical
16-bit Address bus Offset address
to memory
 Cache Memory
c
CPU C a Main external
a c
h memory storage
c e
h
e
• Cache: fast-access memory buffer
• locality principle: programs usually use limited memory areas, in contrast to
totally random access
• spatial: location, address
• temporal: time accessed
• if commonly used memory can be buffered in high-speed cache, overall
performance enhanced
• cache takes form of small amount of store, with hardware support for
maintenance and lookup
• each cache cell saves a cache line - block of main memory (4-64 words)

• cache hit:
• requested memory resides in cache
 Cache
• cache miss:
• requested memory not in cache, and must be fetched from main
memory and put into cache
• unified cache:
• instns, data share same cache
• split cache:
• separate instn, data caches
• parallel access:
• double the bandwidth
• level 2 cache:
• between instn/data cache and main memory
• Cache maintenance algorithms similar in spirit to virtual
memory ideas at operating system level; main difference is
that cache is hardware-supported, whereas v.m. is software
implemented
 Measuring cache
performance
• c - cache access time
• m - main memory access time
• hr - hit ratio ( 0 <= hr <= 1) :
• # cache hits / total memory requests
• mr - miss ratio (1-hr)
• mean access time = c + (1-hr)m

• if hr --> 1 then m.a.t. = c

• if hr --> 0 then m.a.t. = c + m

 Cache Example

• example:
let c = 160 ns
m = 960 ns
h = .90 (common)

mean = 160 + (1-.90)960

= 256 ns

efficiency = c / mean
= 160/256 = 62.5%
 Direct mapping

Main memory
0
1
Cache
0

i mod N i

N-1
M-1

• Direct mapping places each memory block into a specific cache line within a set, allowing no
alternative placements.
• Direct mapping is a procedure used to assign each memory block in the main memory to a particular
line in the cache.
Cache Mapping
• Cache mapping refers to the technique used to determine how data is
stored and retrieved in cache memory.
• It establishes the mapping between memory addresses and cache
locations.

MOD 5 - Memory and Storage Organisation 33

Understanding Direct-Mapped
Cache
• In the direct mapping scheme, we map each block of main memory
to only one specific cache location.
• In this scheme, memory blocks are mapped to cache lines using a
hashing or indexing mechanism.
• When accessing the main memory address, we consider its three
components.
• Those are the tag, the index, and the offset.

MOD 5 - Memory and Storage Organisation 34

Direct Mapped Cache
 Direct mapping
• use a hash function to find cache location
• normally, modulo some bit field of address, then just use
low end field
• cache fields:
• valid bit
• tag - block # being held
• value - data block
• scheme:
• memory request:
• compute cache slot (low n bits)
• check block (tag) field
• hit: return value
• miss: fetch block from memory, give to CPU, and put into that computed
slot (replace existing item if there)
• can occasionally produce thrashing
• eg. addresses that are multiple of cache size (64K) will reside at
same entry
• split instn/data cache helps avoid thrashing
Set associative mapping
• Set-associative mapping allows each word that is present in the
cache can have two or more words in the main memory for the same
index address.
• A Set-Associative Cache is defined as a type of cache memory that
reduces conflicts by organizing data into sets with multiple blocks,
allowing each memory address to map to any one of the blocks within
a set.
• The degree of associativity, denoted by 'N', determines the number of
blocks in each set.

MOD 5 - Memory and Storage Organisation 37

 Set associative mapping
Main memory
0
1
Cache
Set 0 S blocks per set
Set 1
Set i mod (N/S) i

Set N/S - 1
M-1
Set associative mapping
 Set associative mapping
• [4.39]

• use same hash function as direct mapping, except that

each cache slot holds multiple data blocks
• usually max. 4 blocks (“4-way”)
• searching blocks in a slot done associatively:
simultaneous pattern matching
• more flexible than direct: multiple blocks in set
• use smaller tag than associative, therefore cheaper to
implement associative matching
• commonly used in larger systems (VAX 11-780)
• which line should be replaced when slot full?
• eg. LRU (least recently used)
 Writing back to the memory

• only write to memory if cache data modified.

• write back (write-deferred):

• (i) use a modified bit. When swapping a cache slot or ending job, write slot if
its modified bit is set

• write through:
• (ii) whenever modifying data, always write it back to main memory
• have to do this if memory being shared in a DMA or multiprocessing system
 Example: direct mapping
4 byte blocks
1 byte words
8 slots in cache

Example − Consider a cache with = 512 lines, then a line would need 9
bits to be uniquely identified.
• Direct mapping divides an address into three parts: t tag bits, l line bits,
and w word bits.
• The word bits are the least significant bits that identify the specific word
within a block of memory.
Example (cont)
The
End