Constraints (Autosaved)
Constraints (Autosaved)
Tejal Adake
Agenda
Bidirectional constraint
Solve before constraint
Inline constraint
Soft constraint
Disable constraint
Static constraint
Inheritance constraint
Rand case constraint
Bidirectional constraint:
which means constraints on all random variables will be
solved in parallel.
As constraints are considered from all the aspects,
System Verilog constraints are called bidirectional
constraints.
Example:
class MyClass;
rand int a;
rand int b;
constraint bidirectional_c { a + b == 10; }
endclass
class MyClass;
rand int a;
rand int b;
constraint range_c { a + b == 10;
a inside {1, 2, 3, 4, 5};
b inside {5, 6, 7, 8, 9};
}
endclass
Solve Before Constraint
solve before is used inside the constraint block to
specify the order of constraint solving.
If the variables are dependent, due to the bidirectional
nature of constraints value of one variable will influence
the value of another variable
solve before constraints are used to force the constraint
solver to choose the order in which constraints are
solved.
The dependency order of variables should not be
bidirectional
Change the probability of distribution
class MyClass; class MyClass;
rand int unsigned a; rand int unsigned a;
randc int unsigned b; rand int unsigned b;
constraint bidirectional_c { a <b; constraint bidirectional_c { a <b;
b< 10; b< 10;
solve a before b; solve a before b;
} solve b before a;
endclass }
endclass
Rules :
class MyClass;
rand int a;
rand int b; here a is
priority than b
constraint c1 { a + b == 10; }
solve a before b;
endclass
Inline constraint
Till now, what we have seen about writing a constraint in
class. There is a possibility that constraints need to be
modified during randomization.
The important thing to note is that inline constraints do not
override constraints written inside the class.
Any conflict in these constraints leads to randomization
failure.
An inline constraint is written on calling
a randomize() method using the “with” keyword.
Example:
class MyClass;
rand bit [3:0] a;
rand bit [3:0] b;
rand int c; if we try to override the
constraint o/p will be:
constraint c1 { a + b == 10; }
endclass
module test;
MyClass cx;
initial begin
repeat(5) begin
cx=new();
cx.randomize() with {cx.c inside {[1:5]}; cx.a <=10;}; // c.randomize() with {cx.a>10;};
$display("a=%0d b=%0d c=%0d a+b=%0d",cx.a,cx.b,cx.c,cx.a+cx.b);
end
end
endmodule
Soft constraint
sometimes there is a requirement to change constraints in
such a way that it may conflict with constraints inside the
class.
By default, constraints are hard constraints in nature. To
mention constraints as a soft, specifically “soft” keyword has
to be used.
Example: class MyClass;
rand bit [3:0] a;
class MyClass; rand bit [3:0] b;
rand int a; rand int c;
rand int b; constraint c1 { soft a + b == 10; }
rand int c; endclass
constraint c1 { soft a <=10; b>=15; }
module test;
endclass
MyClass cx;
module test; initial begin
Myclass cx; repeat(5) begin
Initial begin cx=new();
cx=new(); cx.randomize() with {cx.c inside {[1:5]}; cx.a >10;};
repeat(5) begin $display("a=%0d b=%0d c=%0d a+b=
cx.randomize() with {cx.c inside {1:5;} %0d",cx.a,cx.b,cx.c,cx.a+cx.b);
cx.a>=10;}; end
$display(“a=%0b b=%0d c= end
%0d”,cx.a,cx.b,cx.c); endmodule
end
end
endmodule
Disable constraint
Constraints in a class can be disabled using the
constraint_mode method call
By default, constraint mode is enabled i.e.
constraint_mode(1)
To disable constraint, constraint_mode(0) is used.
A Constraint needs to be disabled or enabled (if disabled
before) before calling the randomize() method
Syntax:
object.constraint_name.constraint_mode()
class pkt;
randc bit [7:0] addr;
rand bit [31:0] data;
rand bit wr;
constraint c_pkt {addr[7]==1; data>0; wr==1;}
endclass
module ex;
pkt p1;
initial begin
p1=new();
if(p1.c_pkt.constraint_mode()) begin
$display("packet randomization is ON");
repeat(5) begin
p1.randomize();
$display("addr=%0d data=%0dwr=%0d",p1.addr,p1.data,p1.wr);
end
end
p1.c_pkt.constraint_mode(0);
$display("current state of randomization is
%0d",p1.c_pkt.constraint_mode());
end
endmodule
Static constraint
A static constraint is shared across all class instances. It
is similar to a static variable in a class.
Static constraints are useful when you want the
constraint to be applied across all instances of the
class, not just a particular object.
Syntax:
static constraint <constraint name>
{. . .;}
class seq_item;
rand bit [7:0] value1;
rand bit [7:0] value2;
constraint value1_c {value1 inside {[10:30]};}
static constraint value2_c {value2 inside {40,70, 80};}
endclass
module constraint_example;
seq_item item1, item2;
initial begin
item1 = new();
item2 = new();
item1.randomize();
item2.randomize();
$display("Before disabling constraint");
$display("item1: value1 = %0d, value2 = %0d", item1.value1, item1.value2);
$display("item2: value1 = %0d, value2 = %0d", item2.value1, item2.value2);
module constraint_inh;
parent p;
child c;
initial begin
p = new();
c = new();
repeat(3) begin
p.randomize();
$display("Parent class: value = %0d", p.value);
end
repeat(3) begin
c.randomize();
$display("Child class: value = %0d value=%0d", c.value,p.value);
end
end
endmodule
Rand case
Randomly pick one out of many statements
NOTES:
Any branch having 0 weight – not picked but all branch having 0 weight it will throw an error
class pkt;
rand bit [1:0] addr;
endclass
module ex;
pkt p1;
int counter=0,counter1=0,counter2=0,counter3=0;
initial begin
p1=new();
for(int i=0;i<1000;i++) begin
randcase
3:begin p1.addr=3; counter3++; end // 3/10
2:begin p1.addr=2; counter2++; end // 2/10
1:begin p1.addr=1; counter1++; end // 1/10
4:begin p1.addr=4; counter++; end //4/10
endcase
$display("addr: %0d",p1.addr);
end
$display("counter =%0d counter1 =%0d counter2=%0d
counter3=%0d",counter,counter1,counter2,counter3);
end
endmodule
class pkt;
rand bit [1:0] addr;
endclass
module ex;
pkt p1;
int counter=0,counter1=0,counter2=0,counter3=0;
initial begin
p1=new();
for(int i=0;i<1000;i++) begin
randcase
3:begin p1.addr=3; counter3++; end
2:begin p1.addr=2; counter2++; end
1:begin p1.addr=1; counter1++; end
0:begin p1.addr=4; counter++; end
endcase
$display("addr: %0d",p1.addr);
end
$display("counter =%0d counter1 =%0d counter2=%0d
counter3=%0d",counter,counter1,counter2,counter3);
end
endmodule
class pkt;
rand bit [1:0] addr;
endclass
module ex;
pkt p1;
int counter=0,counter1=0,counter2=0,counter3=0;
initial begin
p1=new();
for(int i=0;i<1000;i++) begin
randcase
0:begin p1.addr=3; counter3++; end
0:begin p1.addr=2; counter2++; end
0:begin p1.addr=1; counter1++; end
0:begin p1.addr=4; counter++; end
endcase
$display("addr: %0d",p1.addr);
end
$display("counter =%0d counter1 =%0d counter2=%0d
counter3=%0d",counter,counter1,counter2,counter3);
end
endmodule
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