ADVANCED MICROPROCESSORS

80386
FEATURES
ARCHITECTURE
REGISTER ORGANIZATION
SEGMENTATION AND PAGING
 SALIENT FEATURES OF 80386
 8, 16, 32-Bit Data Types
o 8 General Purpose 32-Bit Registers
 Very Large Address Space
o 4 Gigabyte Physical
o 64 Terabyte Virtual (16k segments)
o 4 Gigabyte Maximum Segment Size
 Integrated Memory Management Unit
o Virtual Memory Support
o Optional On-Chip Paging
o 4 Levels of Protection
o Fully Compatible with 80286
 Object Code Compatible with All 8086 Family Microprocessors
 Virtual 8086 Mode Allows Running of 8086 Software in a Protected and
Paged System
 Hardware Debugging Support
 Optimized for System Performance
o Pipelined Instruction Execution
o On-Chip Address Translation Caches
o 20, 25 and 33 MHz Clock
o 40, 50 and 66 Megabytes/Sec Bus Bandwidth
 Versions: 80386DX, 80386SX
 Numeric Support via Intel387TM DX Math Coprocessor
 Complete System Development Support
o Software: C, PL/M, Assembler
o System Generation Tools
o Debuggers: PSCOPE, ICETM-386
 High Speed CHMOS IV Technology
o 132 Pin Grid Array Package
o 132 Pin Plastic Quad Flat Package
•The processing mode of the 80386 also determines the
features that are accessible. The 80386 has three
processing modes
1. Protected Mode.
2. Real-Address Mode.
3. Virtual 8086 Mode.
 A RC H I T E C T U R E A N D S I G N A L D E S C R I P T I O N

 The Internal Architecture of 80386 is divided into 3 sections.

 Central processing unit
 Memory management unit
 Bus interface unit
 Central processing unit is further divided into Execution unit and
Instruction unit
 Execution unit has 8 General purpose and 8 Special purpose
registers which are either used for handling data or calculating
offset addresses.
Internal architecture of 80386
 REGISTER ORGANIZATION

• The 80386 has eight 32 - bit general purpose registers which may be used as
either 8 bit or 16 bit registers.
• A 32 - bit register known as an extended register, is represented by the
register name with prefix E.
• Example : A 32 bit register corresponding to AX is EAX, similarly BX is
EBX etc.

• The 16 bit registers BP, SP, SI and DI in 8086 are now available with their
extended size of 32 bit and are names as EBP,ESP,ESI and EDI.
• AX represents the lower 16 bit of the 32 bit register EAX.

• BP, SP, SI, DI represents the lower 16 bit of their 32 bit counterparts, and can
be used as independent 16 bit registers.

• The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS.
• The CS and SS are the code and the stack segment registers respectively,
while DS, ES, FS, GS are 4 data segment registers.

• A 16 bit instruction pointer IP is available along with 32 bit counterpart EIP.

•

• Flag Register of 80386: The Flag register of 80386 is a 32 bit register. Out of the 32
bits, Intel has reserved bits D18 to D31, D5 and D3, while D1 is always set at 1.Two extra
new flags are added to the 80286 flag to derive the flag register of 80386. They are VM
and RF flags.
• VM - Virtual Mode Flag: If this flag is set, the 80386 enters the virtual 8086 mode
within the protection mode. This is to be set only when the 80386 is in protected mode. In
this mode, if any privileged instruction is executed an exception 13 is generated. This bit
can be set using IRET instruction or any task switch operation only in the protected mode.
•
RF- Resume Flag: This flag is used with the debug register breakpoints. It is checked at
the starting of every instruction cycle and if it is set, any debug fault is ignored during the
instruction cycle. The RF is automatically reset after successful execution of every
instruction, except for IRET and POPF instructions.
• Also, it is not automatically cleared after the successful execution of JMP, CALL and
INT instruction causing a task switch. These instruction are used to set the RF to the
value specified by the memory data available at the stack.
 • Segment Descriptor Registers: This registers are not available for programmers,
rather they are internally used to store the descriptor information, like attributes,
limit and base addresses of segments.
• The six segment registers have corresponding six 73 bit descriptor registers. Each
of them contains 32 bit base address, 32 bit base limit and 9 bit attributes. These
are automatically loaded when the corresponding segments are loaded with
selectors.
• Control Registers: The 80386 has three 32 bit control registers CR0, CR2 and CR3 to
hold global machine status independent of the executed task. Load and store
instructions are available to access these registers.
• System Address Registers: Four special registers are defined to refer to the
descriptor tables supported by 80386.
• The 80386 supports four types of descriptor table, viz. global descriptor table
(GDT), interrupt descriptor table (IDT), local descriptor table (LDT) and task state
segment descriptor (TSS).
• Debug and Test Registers: Intel has provide a set of 8 debug registers for hardware
debugging. Out of these eight registers DR0 to DR7, two registers DR4 and DR5 are
Intel reserved.
• The initial four registers DR0 to DR3 store four program controllable breakpoint
addresses, while DR6 and DR7 respectively hold breakpoint status and breakpoint
control information.
• Two more test register are provided by 80386 for page cacheing namely test control
and test status register.
•
 A D D R E S S I N G M O D E S O F 80386:

•The 80386 supports overall eleven addressing modes to facilitate efficient execution of higher level
language programs.
• In case of all those modes, the 80386 can now have 32-bit immediate or 32- bit register
operands or displacements.
• The 80386 has a family of scaled modes. In case of scaled modes, any of the index
register values can be multiplied by a valid scale factor to obtain the displacement.
• The valid scale factor are 1, 2, 4 and 8.
• The different scaled modes are as follows.
• Scaled Indexed Mode: Contents of the an index register are multiplied by a scale factor that
may be added further to get the operand offset.
• Based Scaled Indexed Mode: Contents of the an index register are multiplied by a scale
factor and then added to base register to obtain the offset.
• Based Scaled Indexed Mode with Displacement: The Contents of the an index register are
multiplied by a scaling factor and the result is added to a base register and a displacement to
get the offset of an operand.
 D A T A T Y P E S O F 80386:

• The 80386 supports the following data types they are

 Bit
 Bit Field: A group of at the most 32 bits (4bytes)
 Bit String: A string of contiguous bits of maximum 4Gbytes in length.
 Signed Byte: Signed byte data
 Unsigned Byte: Unsigned byte data.
 Integer word: Signed 16-bit data.
 Long Integer: 32-bit signed data represented in 2’s complement form.
 Unsigned Integer Word: Unsigned 16-bit data
 Unsigned Long Integer: Unsigned 32-bit data
 Signed Quad Word: A signed 64-bit data or four word data.
 Unsigned Quad Word: An unsigned 64-bit data.
 Offset: 16/32-bit displacement that points a memory location using any of the
addressing modes.
 Pointer: This consists of a pair of 16-bit selector and 16/32-bit offset.
 Character: An ASCII equivalent to any of the alphanumeric or control characters.
 Strings: These are the sequences of bytes, words or double words. A string may
contain minimum one byte and maximum 4 Gigabytes.
 BCD: Decimal digits from 0-9 represented by unpacked bytes.
 Packed BCD: This represents two packed BCD digits using a byte, i.e. from 00 to 99.
THANK YOU