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6 - Bus System Using Multiplexer (For Numerical Part)

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178 views25 pages

6 - Bus System Using Multiplexer (For Numerical Part)

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kudesiat
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© © All Rights Reserved
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Computer

Organization and
Architecture
BUS SYSTEM USING
MULTIPLEXER
by
Upendra Mishra
(B.Tech., M.Tech. PhD.(P))
KIET Group of Institutions
Contents

MULTIPLEXER

BUS SYSTEM USING MULTIPLEXER


MULTIPLEXER(MUX)
Multiplexer
 Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’ selection
Example: 8x1 Multiplexer
lines and single output line. Input: 8 -> pow(2,3)
 2x1 Multiplexer 4x1 Multiplexer 8x1 Multiplexer Selection lines: 3
Output: 1
16x1 Multiplexer ……. Inputs
8x1 Outputs
Mux
A Select
B
C lines
D

Block Diagram Truth Table


4-TO-1-LINE MULTIPLEXER
Function Table for 4-to-1 Line Multiplexer

The multiplexer is also called a data selector,


since it selects one of many data inputs, and
steers the binary information to the output.
4-TO-1-LINE MULTIPLEXER
Decoder
 Decoder is a combinational circuit that has ‘n’ input lines and 2n data outputs out of which
only ONE output is activated based on ‘n’ inputs. Example: 3*8 Decoder
Input: 3
 2x4 Decoder 3x8 Decoder Output: 8 -> pow(2,3)
4x16 Decoder

Block Diagram Truth Table


BUS SYSTEM USING MULTIPLEXER

A typical digital computer has many registers, and paths must be


provided to transfer information from one register to another.
The number of wires will be excessive if separate lines are used between
each register and all other registers in the system.
A more efficient scheme for transferring information between registers in
a multiple-register configuration is a common bus system.
BUS SYSTEM USING MULTIPLEXER

A bus structure consists of a set of common lines, one for each bit of a
register, through which binary information is transferred one at a time.
Control signals determine which register is selected by the bus during
each particular register transfer.
One way of constructing a common bus system is with multiplexers.
The multiplexers select the source register whose binary information is
then placed on the bus.
Bus System for Four Registers
Bus System for Four
Registers
1.Number of Multiplexer Required= Number of bits in each register
2. Size of Multiplexer = Number of register used
Bus System for Four Registers
Each register has four bits, numbered 0 through 3.
The bus consists of four 4X1 multiplexers each having four data inputs, 0
through 3, and two selection inputs, S1 and S0.
For example, output 1 of register A is connected to input 0 of Mux 1 because
this input is labelled A1.
The MUX 0 multiplexes the four 0 bits of the registers, MUX 1 multiplexes the
four 1 bits of the registers, and similarly for the other two bits.
Bus System for Four Registers
The two selection lines S1 and S0 are connected to the selection inputs of all
four multiplexers.
The selection lines choose the four bits of one register and transfer them into
the four-line common bus. When S1S0=00, the 0 data inputs of all four
multiplexers are selected and applied to the outputs that form the bus.
This causes the bus lines to receive the content of register A since the outputs
of this register are connected to the 0 data inputs of the multiplexers. Similarly,
register B is selected if S1S0=01, and so on.
Bus System for Four Registers

In general, a bus system will multiplex k registers of n bits each to produce an
n-line common bus.
The number of multiplexers needed to construct the bus is equal to n, the
number of bits in each register.
The size of each multiplexer must be k X 1 since it multiplexes k data lines.
Bus System for Four Registers

The transfer of information from a bus into one of many destination registers
can be accomplished by connecting the bus lines to the inputs of all destination
registers and activating the load control of the particular destination register
selected.
GENERAL REGISTER ORGANIZATION Input
Clock

A bus organization
for seven CPU R1 A
R2
registers. R3

R1 R2+R3 R4
B
R5
1. MUX A selector (SELA): R6
to place the content of R2 R7
into bus A . Load
2 . MUX B selector (7 lines)
(SELB): to place the SELA { MUX MUX } SELB

content o f R 3 into bus B


3 . ALU operation selector 3x8
R2
A bus R3
B bus
decoder
(OPR): to provide the
arithmetic addition
A + B. SELD
OPR ALU
4. Decoder destination
selector (SELD): to OPR
transfer the content of
the output bus into R1 Result -> Register Output 20
Problem
Q1.A bus-organized CPU has 16 registers with 32 bits in each. an ALU, and a
destination decoder.
a)How many multiplexers are there In the A bus, and what is the size of each
multiplexer?
b)How many selection Inputs are needed for MUX A and MUXB?
c)How many inputs and outputs are there in the decoder?
d)How many inputs and outputs are there in the ALU for data, including
input and output carries?
e)Formulate a control word for the system if the ALU has 35
operations.
SEL A SEL B SEL D OPR
References

 Computer System Architecture - M. Mano , 3rd Edition.


Thank
You

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