UNIT II

COMBINATIONAL LOGIC
 Combinational Circuits
• A combinational logic circuit has:
– A set of m Boolean inputs,
– A set of n Boolean outputs, and
– n switching functions, each mapping the 2m input
combinations to an output such that the current output
depends only on the current input values
• A block diagram:
Combinatorial
Logic
Circuit

m Boolean Inputs n Boolean Outputs

 Design Procedure
1. From the specifications of the circuit, determine
the required number of inputs and outputs and
assign a symbol to each.
2. Derive the truth table that defines the required
relationship between inputs and outputs.
3. Obtain the simplified Boolean functions for each
output as a function of the input variables.
4. Draw the logic diagram and verify the correctness
of the design (manually or by simulation).
Example: BCD to Excess-3 Code Converter
K-Maps for BCD to Excess-3
Code Converter
Simplified Expressions for
output Variables
Logic Diagram for BCD to Excess-3 Code Converter
Half Adder: A combinational circuit that performs
the addition of two bits is called a half adder.

Truth Table Simplified Boolean Functions

Implementation of Half adder
Full Adder: Combinational circuit that forms the
arithmetic sum of three bits. It consists of three inputs
and two outputs.

Truth Table

Boolean Function
K-Maps for Full Adder
Implementation of Full Adder
Implementation of full adder with two half
adders and an OR gate
Binary Adder: a digital circuit that produces the arithmetic
sum of two binary numbers
It can be constructed with full adders connected in cascade,
with the output carry from each full adder connected to
the input carry of the next full adder in the chain

4-Bit Binary Adder constructed using Full Adders

 Carry Propagation
• In any combinational circuit, the signal must propagate
through the gates before the correct output sum is
available in the output terminals.
• The total propagation time is equal to the propagation
delay of a typical gate, times the number of gate levels in
the circuit.
• The longest propagation delay time in an adder is the time
it takes the carry to propagate through the full adders.
• Since each bit of the sum output depends on the value of
the input carry, the value of Si at any given stage in the
adder will be in its steady-state final value only after the
input carry to that stage has been propagated.
Carry Lookahead Logic
Carry Generate Gi & Carry Propagate Pi
Gi is called a carry generate , and it produces a carry of 1
when both Ai and Bi are 1, regardless of the input carry Ci.
Pi is called a carry propagate , because it determines
whether a carry into stage i will propagate into stage i + 1
Sum & Carry output
Gi and Pi Functions functions using Gi & Pi
 Boolean Functions for the
Carry outputs of each stage
C0 = input carry
C1 = G0 + P0C0
C2 = G1 + P1C1 = G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0
C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0

Since the Boolean function for each output carry is

expressed in sum-of-products form, each function can
be implemented with one level of AND gates followed
by an OR gate (or by a two-level NAND).
Carry Lookahead Generator
Four-bit adder with carry lookahead
 Binary Subtractor
The subtraction of unsigned binary numbers can
be done most conveniently by means of
complements
Subtraction A - B can be done by taking the 2’s
complement of B and adding it to A
The 2’s complement can be obtained by taking
the 1’s complement and adding 1 to the least
significant pair of bits.
The 1’s complement can be implemented with
inverters, and a 1 can be added to the sum
through the input carry.
Four-bit adder–subtractor
(with overflow detection)
• Addition and subtraction operations can be combined into
one circuit with one common binary adder by including an
exclusive-OR gate with each full adder.
• The mode input M controls the operation. When M = 0, the
circuit is an adder, and when M = 1, the circuit becomes a
subtractor.
• Each exclusive-OR gate receives input M and one of the inputs
of B .
– When M = 0, we have B XOR 0 = B. The full adders receive the
value of B , the input carry is 0, and the circuit performs A plus B
– When M = 1, we have B XOR 1 = B’ and C0 = 1. The B inputs are
all complemented and a 1 is added through the input carry. The
circuit performs the operation A plus the 2’s complement of B
• The exclusive-OR with output V is for detecting an overflow.
 Overflow
• Overflow occurs when two numbers (binary or decimal numbers, signed
or unsigned) with n digits each are added and the sum is a number
occupying n + 1 digits.
• Overflow is a problem in digital computers as the result that contains n +
1 bits cannot be accommodated by an n -bit word.
• Computers detect the occurrence of an overflow, and when it occurs, a
corresponding flip-flop is set.
• When two unsigned numbers are added, an overflow is detected from
the end carry out of the most significant position.
• When two signed numbers are added, the sign bit is treated as part of
the number and the end carry does not indicate an overflow.
• An overflow may occur if the two numbers added are both positive or
both negative.
• If carry into the sign bit position and the carry out of the sign bit
position, are not equal, an overflow has occurred.
• If the two carries are applied to an exclusive-OR gate, an overflow is
detected when the output of the gate is equal to 1.
 Decimal Adder

Arithmetic circuits that accept coded decimal

numbers and present results in the same code.
Eg: BCD Adder which performs the arithmetic
addition of two decimal digits in BCD, together
with an input carry from a previous stage.
Since each input digit does not exceed 9, the
output sum cannot be greater than 9 + 9 + 1 =
19, the 1 in the sum being an input carry.
Derivation of BCD Adder
Logic circuit to detect necessary correction
• The logic circuit that detects the necessary correction can
be derived from the entries in the table.
• Correction is needed when the binary sum has an output
carry K = 1.
• The other six combinations from 1010 through 1111 that
need a correction have a 1 in position Z8.
• To distinguish them from binary 1000 and 1001, which also
have a 1 in position Z8, we specify further that either Z4 or
Z2 must have a 1.
• Hence, condition for a correction and an output carry can
be expressed by the Boolean function.
C = K + Z8Z4 + Z8Z2
• When C = 1, it is necessary to add 0110 to the binary sum
and provide an output carry for the next stage.
Block diagram of a BCD adder
 MAGNITUDE COMPARATOR
• A magnitude comparator is a combinational circuit
that compares two numbers A and B and
determines their relative magnitudes.
• The outcome of the comparison is specified by
three binary variables that indicate whether A>B,
A=B, or A<B.
• The circuit for comparing two n-bit numbers has
22n entries in the truth table and becomes too
cumbersome, even with n = 3.
• Digital functions like magnitude comparator
possess an inherent well-defined regularity can be
designed by means of an algorithm.
Algorithm for Magnitude Comparator
• Let the two 4-bit numbers for comparison be
• A = A3 A2 A1 A0, B = B3 B2 B1 B0
• The two numbers are equal if all pairs of significant
digits are equal: A3 = B3, A2 = B2, A1 = B1, and A0 =
B0.
• When the numbers are binary, the digits are either
1 or 0, and the equality of each pair of bits can be
expressed logically with an exclusive-NOR function
as
xi = Ai Bi + Ai’Bi’ for i = 0, 1, 2, 3
• where xi = 1 only if the pair of bits in position i are
equal (i.e., if both are 1 or both are 0).
 Equality Condition
The equality of the two numbers A and B is
displayed in a combinational circuit by an
output binary variable (A=B).
This binary variable is equal to 1 if the input
numbers, A and B , are equal, and is equal to 0
otherwise.
For equality to exist, all xi variables must be
equal to 1, a condition that dictates an AND
operation of all variables:
(A=B) = x3x2x1x0
 In-equality Conditions
• To determine whether A is greater or less than B, inspect the
relative magnitudes of pairs of significant digits, starting from
the most significant position.
• If the two digits of a pair are equal, compare the next lower
significant pair of digits.
• Comparison continues until a pair of unequal digits is reached.
• If the corresponding digit of A is 1 and that of B is 0, then
conclude A > B.
• If the corresponding digit of A is 0 and that of B is 1 then A < B.
• Sequential comparison is expressed logically by the following
two Boolean functions
4-Bit Magnitude Comparator
 DECODERS
• A decoder is a combinational circuit that
converts binary information from n input lines
to a maximum of 2n unique output lines.
• If the n-bit coded information has unused
combinations, the decoder may have fewer
than 2n outputs.
• Decoders are called n-to-m line decoders,
where n is the number of inputs and m is the
number of outputs and m <= 2n .
• Purpose is to generate the 2n (or fewer)
minterms of n input variables.
3-to-8 line Decoder
Logic Diagram of 3-to-8 Decoder
Two-to-four-line decoder with enable input
4X16 Decoder constructed with two 3X8
Decoders
Implementation of Boolean Functions using
Decoders

• A decoder provides the 2n minterms of n input

variables.
• Since any Boolean function can be expressed
in sum-of-minterms form, a decoder with an
external OR gate can implement the function.
• Any combinational circuit with n inputs and m
outputs can be implemented with an n-to-2n-
line decoder and m OR gates.
Implementation of a full adder with a decoder
 Encoder
• An encoder is a digital circuit that performs the
inverse operation of a decoder.
• An encoder has 2n (or fewer) input lines and n
output lines.
• The output lines, as an aggregate, generate the
binary code corresponding to the input value.
• Example: Octal to binary encoder which has 8
input lines and three output lines.
Octal-to-binary Encoder
 Priority encoder
• A priority encoder is an encoder circuit that includes
the priority function.
• The operation of the priority encoder is such that if
two or more inputs are equal to 1 at the same time,
the input having the highest priority will take
precedence.
K-Maps for Priority Encoder
Implementation of 4-input Priority Encoder
 MULTIPLEXER
• A multiplexer is a combinational circuit that
selects binary information from one of many
input lines and directs it to a single output line.
• The selection of a particular input line is
controlled by a set of selection lines.
• No. of Input lines = 2n
• No. of output line = 1
• No. of Selection lines = n
• Bit combinations of selection lines determine
which input is directed to output.
4-to-1 line Multiplexer (4 X 1 MUX)
4 X 1 Multiplexer Block Diagram
Quadruple 2-to-1 line Multiplexer
 Implementing a Boolean function of n variables
with a multiplexer that has n - 1 selection inputs
Consider the Boolean function
F (x, y, z) = (1, 2, 6, 7)
• This function of three variables can be implemented with a four-to-
one-line multiplexer.
• The two variables x and y are applied to the selection lines in that
order; x is connected to the S1 input and y to the S0 input.
• The values for the data input lines are determined from the truth
table of the function. When xy = 00, output F is equal to z because F =
0 when z = 0 and F = 1 when z = 1.
• This requires that variable z be applied to data input 0. The operation
of the multiplexer is such that when xy = 00, data input 0 has a path
to the output, and that makes F equal to z.
• Similarly we determine the required input to data lines 1, 2, and 3
from the value of F when xy = 01, 10, and 11, respectively.
Implement the following Boolean function
using Multiplexer

F (A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)

 Three-State Gates

Two of the states are signals equivalent to logic 1 and

logic 0 as in a conventional gate.
The third state is a high-impedance state in which,
 the logic behaves like an open circuit, which means
that the output appears to be disconnected,
 the circuit has no logic significance, and
 the circuit connected to the output of the three-state
gate is not affected by the inputs to the gate.
Multiplexers with three-state gates
 Demultiplexer
• A demultiplexer is a circuit that receives information from a single line and
directs it to one of 2n possible output lines.
• A decoder with enable input can function as a demultiplexer.
• The selection of a specific output is controlled by the bit combination of n
selection lines.
• The 2-to-4 decoder can function as a one-to-four-line demultiplexer when E
is taken as a data input line and A and B are taken as the selection inputs.
• The single input variable E has a path to all four outputs, but the input
information is directed to only one of the output lines, as specified by the
binary combination of the two selection lines A and B .
• This feature can be verified from the truth table of the circuit. For example, if
the selection lines AB = 10, output D2 will be the same as the input value E ,
while all other outputs are maintained at 0.
• Since, decoder and demultiplexer operations are obtained from the same
circuit, a decoder with an enable input is referred to as a decoder –
demultiplexer .
Binary Multiplier
Four-bit by three-bit binary multiplier
 Parity Bit and Error Detection
A parity bit is used for the purpose of detecting
errors during the transmission of binary
information.
A parity bit is an extra bit included with a binary
message to make the number of 1’s either odd or
even.
The message, including the parity bit, is
transmitted and then checked at the receiving end
for errors.
An error is detected if the checked parity does not
correspond with the one transmitted.
 Parity Generator and Checker
 The circuit that generates the
parity bit in the transmitter is
called a parity generator.
 The circuit that checks the parity
in the receiver is called a parity
checker.
3-bit Even Parity Generator
4-bit Even Parity Checker