Lesson 1.

3: Datatypes and Types of

Description in VHDL & Verilog HDL
CPEHDL 311
VHDL Data types
VHDL is a type oriented language. Many operations cannot be
executed without choosing the right type of data types for the
operands. There are 5 major data types.
1. Scalar type
2. Composite type
3. Access type
4. File types
5. Other types
Scalar type
The values of the scalar object types are numeric. It is sub divided into
8 types:
1. Bit type: the only value used is 0 or 1.
2. Boolean type: the only value used is true(1) or false(0).
3. Integer type: all integer values are used, “range” is used to define
a shorter range of integer, “natural” is used when all values are
positive.
4. Real type: this type accepts fractions.
 Scalar type example
entity ScalarTypeExample is architecture Behavioral of
ScalarTypeExample is
Port (
clk : in bit; -- Clock signal signal internal_count : integer := 0; --
reset : in boolean; -- Reset signal Internal counter

count : out integer -- Output count signal voltage : real := 5.0; --

); Example real value

end ScalarTypeExample; signal status : bit := '0'; -- Example

bit value

Begin
Composite Type
The composite data type is a • Array type: this type is defined by
collection of values. There are 3 using the pre defined word “array”.
composite data types. Arrays can be multi dimensional
(similar to arrays in C).
• Bit vector: this data type
represents a array of bits. It is Ex.
denoted as shown in example. type OneDArray is array (0 to 4) of
I1: in bit_vector(3 down to 0); it has 4 integer; -- 1D array with 5
bits. integers
type TwoDArray is array (0 to 3, 0 to 3)
of bit; -- 2D array (4x4) of bits
 entity RecordExample is
Composite Type Port ( clk : in std_logic;
• Record types: this data type can be reset : in std_logic);
composed of same or different end RecordExample;
data types (similar to structures in
C).
architecture Behavioral of RecordExample is
• Basic Syntax
type StudentRecord is record
type MyRecordType is record name : string(1 to 20);
field1 : type1; age : integer;
field2 : type2; gpa : real;
... end record;

end record;
 File types
Objects of this type can be read and written using built in
functions(similar to files in C).
Example:
process
file_open(input_file, "data.txt", read_mode); -- Open file for reading
for i in 0 to 9 loop
readline(input_file, line_buffer); -- Read a line from the file
read(line_buffer, my_data(i)); -- Read data into array
end loop;
file_close(input_file); -- Close the file
end process;
Summary

o Scalar Types: Basic types for single values (e.g., bit, integer, real).
o Composite Types: Complex types that group multiple values (e.g., array,
record).
o File Types: Allow interaction with external files for data input and output.
 Verilog HDL data types:

SYNTAX REGISTERS
reg my_reg; // A 1-bit register Registers are declared by
reg [7:0] data_reg; // An 8-bit the predefined word “reg”.
register registers store values until they
are updated.
Usage of Register
Registers are commonly used for various purposes in digital design,
including:
Storing State: They hold the state of a system in state machines.
Data Buffers: They can act as temporary storage for data being processed.
Control Signals: Registers can store control signals for different parts of a
circuit.
Verilog HDL data types (cont):

VECTORS The range can be specified in two

ways:
Vectors are multiple bits •Descending Order: reg [7:0]
declared by brackets []. A register or net
can be declared as a vector. my_vector; (from 7 down to 0,
meaning 8 bits).
•Ascending Order: reg [0:7]
my_vector; (from 0 to 7, still 8 bits).
 Verilog HDL data types (cont):

INTEGER
The integer type is a signed, whole Example:
number data type that allows for integer count; // A single
arithmetic operations and is often used integer variable
for loop counters, array indexing, and
other calculations where non-negative integer array[0:9]; // An array of
values are insufficient. 10 integers
Verilog HDL data types (cont):

PARAMETERS Parameters are declared using the

Parameters are constants parameter keyword, followed by the
that can be defined within a name of the parameter and its value.
module, allowing designers to set
Ex:
values that can control various parameter WIDTH = 8; // Declare a
aspects of the module’s behavior parameter named WIDTH with a value
or structure. of 8
parameter DEPTH = 16; // Another
parameter for depth
Usage of parameter
Parameters can be used to define the sizes of data types, array
dimensions, and other configuration values within a module.
They can enhance the modularity of the design, making it easier
to change values in one place without modifying the entire
codebase.
Verilog HDL data types (cont):

ARRAYS
Arrays are used to group • Arrays can be single-dimensional
multiple elements of the same data or multi-dimensional and are
type, enabling the efficient widely used in various digital
organization and manipulation of design scenarios, such as
related data. memory modeling and data
storage.
Example:

reg [7:0] my_array [0:15]; // An array of 16 elements, each 8 bits wide

Types of Description in VHDL and Verilog
In both VHDL and Verilog, types of description serve specific
purposes that facilitate the design, simulation, and synthesis of digital
circuits. Here’s a breakdown of their purposes in each language:
Behavioral description Example of Behavioral Description—VHDL and Verilog
--is based on the manner in which VHDL Behavioral Description
outputs behave with the inputs. In
VHDL the architecture includes entity half_add is port (I1, I2 : in bit;
the keyword “process”. In Verilog O1, O2 : out bit);
“always” or “initial” is used.
end half_add;
architecture behave_ex of half_add is
begin O1 <= I1 xor I2 after 10 ns;
O2 <= I1 and I2 after 10 ns;
end process;
end behave_ex
Structural description Pure Structural Description HDL
VHDL Structural Description
-- In this description the entire entity system is

system is modeled as port (a, b : in bit;

sum, cout : out bit);
components or gates. The end system;
description is identified by the architecture struct_exple of system is
presence of the key word
component xor2
“component” in architecture in --The above statement is a component
VHDL. In Verilog it is identified statement
port(I1, I2 : in bit;
by gates construct eg and, or. O1 : out bit);
end component;
component and2
port(I1, I2 : in bit;
O1 : out bit);
end component;
begin
X1 : xor2 port map (a, b, sum);
A1 : and2 port map (a, b, cout);
end struct_exple;
 Data Flow Description
Ex:
Data flow description shows entity mux2to1 is
how the signals flow from the Port ( a : in STD_LOGIC;
inputs to the output. The data b : in STD_LOGIC;
flow statements are concurrent. sel : in STD_LOGIC;
The description usually has out : out STD_LOGIC);
Boolean expression of its end mux2to1;
outputs.
architecture DataFlow of mux2to1 is
begin
out <= (a and not sel) or (b and sel); --
Data flow description
end DataFlow;
 Summary
o Behavioral Description: Focuses on what the design does (e.g., adding
numbers, calculating sums).
o Structural Description: Focuses on how components are connected (e.g.,
wiring gates together in a full adder).
o Data Flow Description: Focuses on the flow of data through combinational
logic (e.g., multiplexing signals).
Simulation and Synthesis
Simulation and synthesis are two fundamental processes in VHDL that play
crucial roles in the design and implementation of digital circuits.
The steps involved in simulation and synthesis are as follows:
1. Choose a language to describe the system.
2. Choose the style of description.
3. Write the code. Don’t forget to attach necessary packages to VHDL code.
4. Compile using the compiler.
5. After successful compilation check whether the code describes the system exactly.
6. After the code is verified, then compiler code can be synthesized.
7. The simulator is a cad tool that converts compiler code and generates a net list.
8.This net list is to be downloaded on to a chip usually a FPGA.
End of Lesson 1