2021 1st International Conference on Power Electronics and Energy (ICPEE-2021)

An Optimize Configuration of H-Bridge Multilevel

Inverter
Sushree Smrutimayee Barah Sasmita Behera
Department of Electrical Engineering Department of Electrical and Electronics Engineering
Veer Surendra Sai University of Technology, Burla Veer Surendra Sai University of Technology, Burla
Sambalpur, India Sambalpur, India
[email protected] [email protected]

Abstract— A traditional H-bridge inverter requires a research of inverters [3] [4]. Baker and Banister [5]
minimum of four controllable switches and this multiplies with pioneered the series H-bridge inverter. The demerits of DC
the levels in the inverter output voltage goes up. This work and FC topologies, for instance, additional clamping diodes
represents an improved multilevel inverter with a reduced and capacitors are overcome by a proposed CHB inverter
number of switches. An improved structure using the sub-
[6]. It can give high output power from a medium-voltage
multilevel concept is proposed for a five-level inverter. This
source. Higher voltage can be generated using the lower
2021 1st International Conference on Power Electronics and Energy (ICPEE) | 978-1-7281-8774-7/21/$31.00 ©2021 IEEE | DOI: 10.1109/ICPEE50452.2021.9358533

modified H-bridge inverter uses the same level of an inverter

with a 25% reduction in the number of switches. This results in rating devices. The control of switches in this converter is
reduced switching losses, installation cost, and converter cost. simple and easy to construct. A survey on multilevel
Special care is taken to obtain an optimal number of switches. inverter configuration, control, and application, and an MLI
The proposed inverter is simulated for a five-level using with reduced number switches is described [6]. Because of
Matlab/Simulink with phase disposition pulse width its isolated dc sources, cascaded inverters are appropriate to
modulation (PDPWM) control for both resistive and resistive- interface photovoltaic generation to an ac grid for power
inductive load. A comparison between conventional and quality management [7]. They are suitable for regenerative-
modified H-bridge inverter is shown.
type motor drive applications, fuel cell-based electric
Keywords—cascaded H-Bridge Multilevel Inverter, five-level
vehicles. Potential applications include electric and hybrid
inverter, modified 5-level inverter, THD power trains. A review of MLI configuration was brought
by Pharne [8]. An MLI with a reduction in the number of
switches was described by Ebrahimi et al [9]. The topology
I. has multiple bridge inverters with a sub-multilevel concept.
INTRODUCTION Further development in MLI configuration’s design and
A two-level inverter has two different output voltages and implementation was proposed by Najafi [10], Nedumgatt
is the simplest one. But the ac output is rectangular with [11]. A CHB configuration with a reduction of switches
high total harmonic distortion (THD) whereas the load count is described by Ebrahimi et al. [12]. A survey of
needs sinusoidal voltage. Multilevel inverter (MLI), a step multilevel inverter configurations, control, applications was
ahead of the two-level inverter tends to reduce this effect. It made by Rodriguez et al. [13]. A CHB with regeneration
does so by using many low rated dc voltage sources as input capability and a smaller number of switches was dealt with
for the desired ac voltage output. So, in a multilevel by Lezana et al. [14]. In a similar context, Babaei [15]
inverter, the output voltage is stepped more than twice. As proposed CHB MLI for high-voltage applications.
the level increases in the multilevel inverter, the waveform Looking into the main advantages, owing to its modular
is smoother than the two-level inverter. MLI has two arrangement and absence of energy-storing elements like
classes; current source inverter and voltage source inverter. capacitor a CHB MLI is used in this study. A new method is
In the former, a short circuit in the circuit can cause a very proposed as a modified H-bridge inverter having similar
high fault current which will damage any other types of stepped output voltage using a smaller number of switches.
equipment connected to the circuit. Hence, multilevel This reduction in switches count will result in reducing
voltage source inverters are preferred [2]. There are four switching losses, converter cost, and installation cost.
types of MLI topologies; neutral point clamped (NPC), Section 2 embodies the conventional and modified CHB
diode clamped (DC), flying capacitor (FC), and cascaded H- structure for a 5-level inverter, followed by the modulation
bridge (CHB) multilevel inverter. Cascaded H-bridge technique in section 3 and the simulation results, and finally,
multilevel inverters have preferably low THD [1]. The some conclusions are drawn.
difference between several topologies of MLI lies in the
source of input voltage and the mechanism of switching. II. 5-LEVEL CHB CONFIGURATION
MLI is used in power intense and high voltage
applications. The industry demands additional solutions of A. Conventional CHB MLI
high dv/dt resulting in voltage doubling in motor output, Multilevel inverters are used in power conversion
compliance of % THD, high electromagnetic interference because of its output voltage and current have improved
(EMI) and high common-mode voltages which trigger waveforms. For K sources in a CHB MLI then the output
voltage will have m steps. The relations are
The authors acknowledge the Dept. of EE and EEE, VSSUT, Burla,
m=2K+1 (1)
and TEQIP-III, India for support and funding.
No of source/No of bridges (K)=(m-1)/2 (2)
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No of switches(n)=(mX2)-2 (3)
(4)
Max voltage=KXVdc
Here,
m=no of output voltage level
K=no of bridges
N=no of switching device
Fig.1, shows the CHB MLI with individual units in

Fig. 2. Model of 5-level conventional CHB configuration

C. Modified Configuration
A new sub-multilevel inverter structure is illustrated
herewith that uses a reduced count of IGBTs. Fig. 3 depicts
its elementary configuration. It has a voltage source and two
switches in place of four switches of a bridge. Both the
switches cannot be on together at a time. If this happened

Fig. 1. Structure of cascaded H-bridge MLI

cascade that consist of separate dc sources (SDCS). From

each dc source, ac output voltage is generated that has three
steps +Vdc, 0, and –Vdc. Each H-bridge inverter consists of 4 switches
normally. Conduction of S1 and S4 gives out voltage +Vdc whereas
Fig. 3. Structure of sub-multilevel inverter
conduction of S3 and S2 gives out a voltage is –Vdc. When all the
switches in the unit conduct, the output voltage is zero. As the
output voltages are in series the MLI output aggregates the
cell outputs.
B. Conventional 5-level CHB Configuration
The 5-level CHB inverter has two cascaded H-bridge
units as illustrated in Fig. 2. As per (1)-(4), the cascaded 5-
level bridge inverter uses
Vo 2 separate dc sources =V and 8o2
o1+V
IGBTs. The output voltage is expressed as
(5)
Where Vo1 and Vo2 are the output voltages of the two units
respectively. In a 5-level configuration the number of steps
m is 5. The max voltage Vmax is 2Vdc if both the units have
TABLEsources
identical I. SWITCHING
of Vdc. TheSTATE
switching 5-LEVEL
table
FOR THE switches in the
for theCONVENTIONAL
CONFIGURATION [16]
H-bridge 5-level configuration in Table I.
Modes S1 S2 S3 S4 S5 S6 S7 S8
Fig. 4. Structure for generating full-cycle ac output voltages in
2Vdc on off off on on off off on sub- multilevel inverter
Vdc on off off on off off on on
0 off off off off off off off off then a short circuit occurs. These sub-multilevel inverters
-Vdc off on on off off off on on
-2Vdc
joined in succession form a cascaded sub-multilevel
off on on off off on on off

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inverter. The dc voltage sources associated with each sub-
multilevel inverter have the same value. This structure has
either zero and positive values of output. Fig. 4 shows the
configuration which has both +ve and -ve values in output
ac. This is because of the full-bridge topology added. S1, S2 are

switched on together and conduct for 0<t<T/2 and the output

voltage is Vo. At t=T/2 S1, S2 are gated off and S3, S4 conduct for

T/2<t<T and the output voltage is -Vo, where T is the time

period.
D. Modified 5-level CHB Configuration
The higher the voltage level, the no of switches required
is higher. So, switching losses, costs, and complexity also
increase. By using the modified multilevel inverter with less
no. of switches the efficiency of the system increases. Fig. 5
shows the modified 5-level cascaded multilevel inverter Fig. 6. Model of the PDPWM technique for 5-level cascaded inverter
which has 6 no. of IGBTs and 2 voltage sources. Here the
output voltage step at 2Vdc, Vdc, -2Vdc, -Vdc. Table II shows the on
This modulation imparts less THD for the line to line output
voltages.
and off period of the switches of the modified 5-level
inverter.
IV. SIMULATION RESULT
The conventional 5-level inverter and modified 5-level
inverter are chosen for comparison of performance in this
work. A 10 V dc power source is used along with a load
resistance 10 Ω and an inductance 100µH. Both
conventional and the modified topologies are simulated to
judge their performance with resistive (R) and resistive-
inductive (RL) load. With R load, the voltages are shown in

Fig. 5. Structure of modified 5-level inverter

TABLE II. SWITCHING STATE FOR THE MODIFIED 5-LEVEL

CONFIGURATION Fig. 7. Load voltage of conventional 5-level configuration
Modes S1 S2 S3 S4 S5 S6

2Vdc off on on off off on

Vdc on off on off off on

0 off off off off off off

-Vdc on off off on on off

-2Vdc off on off on on off

III. MODULATION TECHNIQUE

Fig. 8. Load voltage of modified 5-level configuration
The switches of the multilevel inverter start working
when they get a pulse. There are many techniques to
generate the gate pulse. In this work, the pulse width
modulation (PDPWM) technique is used. In this method, a
sine wave is compared with the triangular wave and then
produces the gate signal (Fig. 6). m-1 no. of the triangular
wave is required (where m is the no of output voltage level).
This method reduces unwanted harmonics from the output
voltage. Fig. 9. Load current of conventional 5-level configuration

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Parameters Conventional Modified Patent 3 867 643, 1975.
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2
8
2
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