Antenna EM Latchup
Antenna EM Latchup
Antenna EM Latchup
Antenna Effect :
• The antenna effect occurs mainly due to the excessive accumulation of charges on a metal interconnect
connected to the gate of transistors during the plasma etching of the metal interconnect.
• The amount of accumulated charge depends on the area of the metal interconnect connected to the
gate.
• The excessive accumulated charges get discharged through the thin gate oxide and it causes permanent
damage to the gate oxide.
Antenna Rule :
Antenna ratio is the ratio of the metal area connected to the gate to the total area of the gate.
Reason of EM:
High Current Density (J) : I/A
How is it done
• Semiconductor fabrication companies provide guidelines for the maximum value of current allowed
through a metal wire/via at a particular temperature. This maximum allowed current is called
Electromigration limit. It is defined in the Technology file or Design Rule Check (DRC) book provided by
the fabrication company.
• Interconnects in the design are analyzed for their AC current carrying capacity and is compared with
the maximum value of current limit specified by the foundry. If it exceeds, we see an electromigration
violation.
• The interconnects are tested under stress at extreme PVT conditions to predict the life expectancy of
the design under real conditions.
EM failure mechanism :
• Timing failure :
• narrowing the wire will increase wire resistance, which may cause a timing failure if a signal no longer
propagate within the clock period.
• Function Failure :
• Electromigration will continue until the wire completely breaks, allowing no further current flow and resulting
in functional failure.
Fixing Method
• Increase wire width:
• By increasing the width of the violated net. Increase in metal width results in lower current density which fixes
EM violations.
PNP transistor
• Emitter-drain/source of the P channel Mosfet
• Base- N well in which the complementary P-channel Mosfet is located.
• Collector – p substrate
• Thyristor/SCR/PNPN diode
• Anode- drain/source of the p channel mosfet
• Cathode : drain/source of the N-channel mosfet
• Gate –p substrate
• Solution :
• Surrounding PMOS and NMOS transistors with an insulating oxide layer (trench). This breaks parasitic
SCR structure.
• Latchup Protection Technology circuitry which shuts off the device when latchup is detected.
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