Measurement and

Instrumentation
Data Converters

Dr. M. Zaigham Abbas Shah

Many sensors and actuators are analog!

Strain Gauge
Solenoid
Valve

Thermistors
Thermocouple

 In order to use these with digital devices, we need

a way to convert digital data in to analog and the
other way round
Data Converters
 A data converter is an essential part of a Data
Acquisition System (DAS)

 They provide the link between the digital

processing world and the analog real world

 Data converters can be used to perform both

analog to digital conversion or digital to analog
Digital to Analog Converters(DACs)

 A device used to convert a Digital Number (binary 0’s

and 1’s) in to a proportional Analog Voltage or
Current.

 It scales the analog output to zero when all inputs are

zero and viceVout
versa, mathematically
Vref (bn  ....  b0 2  ( n  1) )

where Vout is the Analog output voltage, Vref is the

reference voltage which sets the range of analog
output voltage
Vref
Vout  n * Input ( Decimal )
 The output equation 2 can also be written as
 The output of the DAC is therefore a multiple or fraction
of the reference voltage
Vref
 The term2n is also called the Resolution which is the
analog voltage per bit increment, mathematically
Vref
Re s  n
2
 The accuracy of this function determines the linearity of
the DAC

 The smaller the reference voltage and greater the

number of bits of the DAC, better is the resolution
 The input/output characteristics of a linear 3-bit ideal
DAC are shown below

where ∆ is the resolution

 The maximum quantization error is equal to half the
value of the resolution ∆ /2.

 The dynamic range is defined as the ratio of the

largest to the smallest resolvable value and is given as
6.02n dBs (. It describes the ‘weight’ of the LSB.

 The full scale output of a DAC is the maximum voltage

it can produce at its output. It is given as .

 Range of operation of a DAC is the swing of the analog

output for the least to full-scale digital input word.
Bipolar DACs
 Output voltage can be negative as well as

positive

 Mathematically its output equation can be written

N 1
as Vout  n Vref  Vref
2 2
DAC structures

 High Speed
• Binary Weighted DAC
• Segmented DAC
• Delta Sigma DAC

 High Resolution
• R-2R DAC
• PWM DAC (won’t be discussed)
• Integrating DAC (won’t be discussed)
• Weighted Capacitor DAC (won’t be discussed)
 Binary Weighted (R/2nR) DAC

 A variation of the Opamp summer amplifier and

works on the principle of weighted current division

 The current is weighted by means of resistors whose

values represent bits of the input digital number
 The current from each of the resistors is summed by the
OpAmp to produce a corresponding voltage

 The output of the binary weighted DAC follows the

equation of the summer amplifier which for the DAC
becomes

 A problem with the binary weighted DAC is that as the

resolution is increased, the number of resistors
increases which increases the power dissipation of the
DAC, also due to resistor tolerance, inaccuracies also
increase.
R2nRDac.DSN
R/2R DAC

 The Binary Weighted DAC required resistors with many

unique values(one per bit) thus manufacturing is a
problem

 The R/2R DAC eliminates this ‘spread’ in resistor values

by using a R/2R ladder network

 This DAC type can work in

voltage as well as current
mode as opposed to voltage
mode only in the
binary weighted DAC

R2RDac.DSN
 The binary weighted DAC scales the current/voltage
from the reference voltage proportional to binary
weights of the bits. As an example

 The current mode R/2R DAC capability to drive loads

directly as it has a current steering architecture
Comparator

 Used to perform comparison of two analog voltages

 Utilizes the very high open loop voltage

gain of the opamp. Due to the high
gain of the opamp, a slight
difference between the input
terminals results in the output
saturating to either the positive
supply(vcc) or the negative supply(vee)

 One of the inputs is given the input

voltage and the other is given a
reference voltage
Where does the simple comparator fail?

 The problem with the simple analog comparator is that

in a noisy environment, when the input signal crosses
the threshold level, the output might have multiple
transitions

What to do?

 Use positive feedback to add ‘hysteresis’ i-e have

multiple
threshold values, a lower threshold and an upper
threshold
Schmitts Trigger/ Hysteresis Comparator

 Uses positive feedback to define two

threshold values

 Introduces noise immunity to

comparators
  When the input voltage comes to a value with in the
hysteresis window, the output maintains its previous
state unless it goes below the lower threshold
value(making the output go to the –ve supply rail) or
goes above the upper threshold level(making the
output go to the +ve supply rail)

 When the output is at ground(i-e the input voltage is

greater than the reference voltage[Vref] i.e.
Vin>Vref ) ,Vref is given by the equation
R 2 || R3
Vref Vcc *
R1  R 2 || R3

Reading: Application Note: Hysteresis in Comparators

 If the output is at Vcc (i-e the input voltage is less
than Vref). Vref is formed by two parts
Vref Vref 1(due _ to _ Vcc)  Vref 2(due _ to _ Vout )

Vout
 By superposition, disconnecte

Vref1 is found by deactivating Vout

R 2 || R3
Vref 1 Vcc *
R1  R 2 || R3
 Vref2 can be found by deactivating Vcc Vcc
disconnected

R1 || R 2
Vref Vout *
( R1 || R 2)  R3

 Therefore, Vref becomes

R 2 || R3 R1 || R 2
Vref Vcc *  Vout *
R1  R 2 || R3 ( R1 || R 2)  R3

 Thus, the additional voltage, increases Vref required to bring

change thus ensuring that there are no transitions due to noise
Analog to Digital
Conversion
 Analog to Digital conversion is the reverse
process of Digital to Analog conversion

 The process of analog to digital conversion

consists of three stages
 Sampling
 Quantization
 Coding
 Sampling
 A continuous signal is sampled in time to form a discrete
time
 Sampling is done at a constant rate following the Nyquist
Sampled Signal
theorem 0.9
Continuous signal
Sampled signal
0.8

0.7

0.6
Amplitude

0.5

0.4

0.3

0.2

0.1

0
0 2 4 6 8 10 12 14 16 18 20
Time
 Quantization
 Quantization is the process of converting a continuous
valued signal in to a discrete valued signal
 This involves the mapping of the possibly infinite values
that analog signals can have in to a discrete set of
values 1
Sampled Signal

0.9

0.8

0.7 Continuous signal

Sampled signal
0.6 Quantized signal (3-bit)
Amplitude

0.5

0.4

0.3

0.2

0.1

0
0 2 4 6 8 10 12 14 16 18 20
Time
 Encoding
 Encoding is the process of representing quantized amplitudes
using some numeric combination
 In most cases this means just representing the amplitudes
with its binary equivalent

 Sampling is performed through a sample and hold

amplifier which in the simplest case can be a capacitor
chosen to hold the voltage long enough for the
subsequent quantization stage to read the signal.

 In this subject we concern ourselves with architectures

pertaining to quantization.
 Most sensors have an analog output

 It finds a binary number which is the closest

approximation to the fraction formed by the input
voltage and the reference
V
bn  ....  b0 2  n  in
Vref
 ADC Structures

 Some typical structures

 High Resolution
• Parallel-Feedback(Successive Approximation) ADC
• Ramp ADC
• Delta Sigma ADC

 High Speed
• Flash ADC
• Pipeline ADC (wont’ be discussed)
• Sub-range ADC (wont’ be discussed)
• Folding ADC (wont’ be discussed)
Parallel-Feedback (Successive Approximation) ADC

 The SAR ADC is a very popular ADC especially as an on-

chip ADC in microcontrollers and offer sampling
frequencies of up to a few MSPS

 It consists of a comparator, a DAC and a special logic

counting network (Successive Approximation Register)

 On a conversion start command, the comparator compares

the input voltage and drives the Logic counter network,
the output of which is connected to DAC.

 The SAR starts from the MSB and one by one checks the
bits by turning them On or Off up till the LSB
 The output of the DAC is
connected to the comparator
and serves as a reference
to check whether the output
of the SAR through the DAC

 The comparator indicates

when the two signals are same
or with in a resolution of the
input voltage thus stopping the
Logic counting network
 If the value is less than the analog input voltage, the value
is left set, otherwise it is reset

 This way by successively changing the bit values, the

digital combination of the analog input voltage is
determined.

 SAR ADCs require N SAR steps for an N bit conversion as

each bit needs to be set or reset appropriately

 The SAR is basically a quantizer and requires that the input

voltage remain constant for the entire time of conversion
Ramp/Integrating ADC

 The integrating ADC eliminates the DAC in ADCs and

is popular for applications where low conversion rates
are acceptable

 These are based on indirect conversion, here the

analog input voltage is converted in to a time period
and then in to a digital number

 It consists of a an Opamp integrator which produces

a sawtooth waveform. This is compared against an
analog input by a comparator. The time it takes for
the sawtooth wave to exceed the input voltage is
measured by means of a counter timed from a crystal
oscillator. The output of the counter is the digital
 The integrating ADC eliminates the need for a sample
and hold amplifier

 The single slope ramp ADC suffers from calibration

drift , a better version is the Dual slope ramp ADC
discussed next
 In the Dual slope Ramp
ADC, the integrator is
first switched to a
negative input voltage
(producing an
increasing ramp) for
time T1, giving the
1
outputV1  or,
RC 
Vx dt

since Vx is constant,
1
V1  T1Vx
RC
 After T1, the input switches to the Vref by the logic
control network which is positive hence producing a
negative ramp. The voltage at the output decreases
as follows 1
RC 
V2 V1  VR dt
After T1
 or
1 1
V2  T1Vx  t xVR
RC RC

 A counter is started at the end of T1 and

it counts till the comparator indicates V2 to be zero.
At this time, Vx is given
tx by
Vx  VR
T1

 Thus the time for which the counter counts(tx) is

proportional to the input voltage (Vx).

 As observed the output expression is free from R and C

 Flash ADCs

 These are the fastest ADCs available and are also used
in microcontrollers as built in units

 Consist of three components, resistors, comparators

and a priority encoder

 For an N bit structure, the flash ADC requires 2N

resistors, and 2N-1 comparators and a priority encoder
(Simulation 2-bit Flash ADC)

 The use of so many components limits the resolution

which is possible
Flash ADC.DSN
 A fixed Vref is provided to the negative input of the
first high speed comparator and each one lower down
will have a reference voltage one LSB less than the
upper one

 The analog input voltage to be converted is given as

an input to all the comparators at once.

 The outputs of the comparator are connected to the

priority encoder, the priority encoder will output the
binary combination of the highest order bit which is
the digital approximation of the analog voltage
 Since flash ADCs require uses a large number of
resistors and comparators, it is not suited for
large resolutions

 Also, due to resistors, the voltage reference

supply has to be able to source quite a significant
amount of current
Delta Sigma ADCs
 Oversampling
 For a signal of frequency Fa sampled with a
frequency of Fs, the magnitude spectrum
can be drawn as
 When the same signal is oversampled, say by
a factor of k, the quantization noise spreads
out thereby reducing the average noise level
 A Delta-Sigma ADC consists of a sigma-delta
modulator and a digital decimator.

 Sigma-Delta modulator consists of a difference

amplifier, an integrator, a comparator and a 1-bit
DAC.
 The DAC switches between +Vref and –Vref.

 The input is provided to the difference amplifier which is

also provided the output of the DAC. The integrator
processes this output and passes it on to the comparator
which compares it with 0v and produces a ‘1’ or ‘0’ as an
output. This is given to the DAC and the Digital filtering
and Down-sampling unit.

 The pattern of the signals repeats after every 16 samples.

 The Digital filtering and Down-sampling unit is used to

remove the remnant quantization noise that remains after
oversampling.
Operation E.g (X=5/8 of
Vref)
Delta Sigma DAC
 The delta-sigma DAC is the reverse process of the
delta-sigma ADC

 The input digital stream is first up-sampled and

then noise-shaped by the sigma-delta modulator.
The DAC as before shifts data between +Vref and
–Vref which is then filtered and averaged by
means of a low pass filter.
 Any questions?

This lecture has been made from the book PC-Based

Instrumentation: Concepts and Practice by M. Mathivanan