COMBINATIONAL AND

SEQUENTIAL CIRCUITS
COMBINATIONAL AND SEQUENTIAL
CIRCUITS

After completing this chapter, you will be able to:

• Define the Combinational and Sequential Difference and there applications

in digital systems
• Define the terms adder, Mux Dmux, Alu, Latch, Flip-Flop
Digital Design

Digital electronics, or digital (electronic) circuits,

represent signals by discrete bands of analog levels, rather
than by a continuous range.

 What are the different categories

Digital Design

Digital electronics, or digital (electronic) circuits,

represent signals by discrete bands of analog levels, rather
than by a continuous range.

Combinational
Sequential
Combinational Logic

 Combinational Logic Circuits are made up from

basic logic NAND, NOR or NOT gates that are
"combined" or connected together to produce more
complicated switching circuits. These logic gates are
the building blocks of combinational logic circuits.
Classification of Combinational Logic
 Sequential Logic Representation

 Unlike Combinational Logic circuits that change state depending upon the
actual signals being applied to their inputs at that time, Sequential Logic
circuits have some form of inherent "Memory" built in to them as they are
able to take into account their previous input state as well as those actually
present, a sort of "before" and "after" is involved with sequential circuits.
 In other words, the output state of a "sequential logic circuit" is a function of
the following three states, the "present input", the "past input" and/or the
"past output". Sequential Logic circuits remember these conditions and stay
fixed in their current state until the next clock signal changes one of the
states, giving sequential logic circuits "Memory".
 HALF ADDER
• Logic device that adds
Input Output Logic
two binary numbers Symbol:
A  (sum)
• Only adds Least Half
Significant Digit (LSD) B Adder C0 (carry out)
column (1s column) in
binary addition

Logic
Diagram:

Half-adder truth table and implementation

S = A`B+AB` = A⊕B

C = AB
o To implement half adder using NAND gates; we
require 5 NAND gates.
 FULL ADDER
Used for adding binary place values other than the 1s place

Input Output
Logic Cin  (sum)
Symbol: Full
A
B Adder C0 (carry out)

Logic
Diagram:
 Full Adder
• Sum S X
Adding two single-bit binary values, X, Y
XY
with a carry input bit C-in produces a C-in 00 01 11 10
sum bit S and a carry out C-out bit. 0 2 6 4
Full Adder Truth Table 0 1 1
Inputs Outputs 1 3 7 5
1 1 1 C-in

X Y C-in S C-out
0 0 0 0 0 Y
S = X’Y’(C-in) + XY’(C-in)’ + XY’(C-in)’ + XY(C-in)
0 0 1 1 0 S = X Å Y Å (C-in)
0 1 0 1 0 Carry C-out X
0 1 1 0 1 XY
1 0 0 1 0 C-in 00 01 11 10
0 2 6 4
1 0 1 0 1 0 1
1 1 0 0 1 1 3 7 5
1 1 1 1 C-in
1 1 1 1 1
S(X,Y, C-in) = S (1,2,4,7) Y
C-out(x, y, C-in) = S (3,5,6,7) C-out = XY + X(C-in) + Y(C-in)
 Full Adder Circuit Using AND-OR

X’ X’Y’C-in
X Y’
X X’ C-in

X’
Y
X’YC-in’ Sum S
Y C-in’
Y Y’ X
Y

C-in C-in’ XY’C-in’

C-in C-in’ X
Y
C-in’ XYC-in

X Y X XY
Y
Full
C-out C-in X
XC-in
Adder C-out
C-in
Y
S
C-in YC-in
 Cont..

Sum-2 gates
Carry 3- gates
 HALF SUBTRACTOR
Subtracts LSD column in binary subtraction

Input Output
Logic A Di (difference)
Symbol: Half
Subtractor
B B0 (borrow out)

Logic
Diagram:
 FULL SUBTRACTOR

Input Output
Logic Bin Di (difference)
Symbol: Full
A
Subtractor
B B0 (borrow out)
 Full Subtractor
Difference D X
XY
 Subtracting two single-bit binary values, Y, B-in from
B-in 00 01 11 10
a single-bit value X produces a difference bit D and a 6
0 2 4
borrow out B-out bit. This is called full subtraction. 0 1 1
Full Subtractor Truth Table 1 3 7 5
Inputs Outputs 1 1 1 B-in

X Y B-in D B-out Y
0 0 0 0 0 S = X’Y’(B-in) + XY’(B-in)’ + XY’(B-in)’ + XY(B-in)
S = X Å Y Å (C-in)
0 0 1 1 1
0 1 0 1 1 Borrow B-out X
0 1 1 0 1 XY
1 0 0 1 0 B-in 00 01 11 10
0 2 6 4
1 0 1 0 0 0 1
1 1 0 0 0 1 3 7 5
1 1 1 1 B-in
1 1 1 1 1
Y
S(X,Y, C-in) = S (1,2,4,7)
B-out = X’Y + X’(B-in) + Y(B-in)
C-out(x, y, C-in) = S (1,2,3,7)
 Full Subtractor Circuit Using AND-OR
X X’ X’Y’B-in
X X’ Y’
B-in

Y X’
X’YB-in’ Difference D
Y
Y Y’ B-in’
X
B-in Y
B-in B-in’ B-in’ XY’B-in’

X
Y
B-in’ XYB-in

X Y X’ X’Y
Y
Full
B-out B-in X’
X’B-in
Subtractor B-out
B-in
Y
D
B-in YB-in
 Full Subtractor Circuit Using XOR

Y Difference D
X Y B-in

Full X’ X’Y
B-out B-in
Subtractor Y

X’
X’B-in
B-out
D B-in
Y

B-in YB-in
Full Subtractor
 Addition

 Adding bits:
 0+0= 0
 0+1= 1
 1+0= 1
 carry
1 + 1 = (1) 0
 Adding integers:
1 1 0
0 0 0...... 0 1 1 1 two = 7ten
+ 0 0 0...... 0 1 1 0 two = 6ten
= 0 0 0 . . . . . . 1 (1)1 (1)0 (0)1 two = 13ten
 Ripple Carry Adder (RCA)

x3 y3 x2 y2 x1 y1 x0 y0

cout=c4 FA FA FA FA c0=cin

s3 s2 s1 s0

Real Goal: Make the fastest possible carry path

 Subtraction
001= 1
111 = 7
110 = 6

Generally we work on present and past inputs , not on future inputs

 Subtraction
001= 1 001
111 = 7 111
110 = 6
 Subtraction
X Y B-in D B-out
001= 1 001 0 0 0 0 0
111 = 7 111 0 0 1 1 1
0 1 0 1 1
110 = 6 1 0 0 1 1 0 1
1 0 0 1 0
10 10 1 0 1 0 0
1 1 0 0 0
01 01 1 1 1 1 1

1
0 1 1 0 = 6

1
In subtraction also borrow will be passed to next stage like addition
Complements

 They are used to simplify the subtraction operation

 Two types (for each base-r system)
• Diminishing radix complement (r-1 complement)
• Radix complement (r complement)

For n-digit number N

n
(r  1)  N r-1 complement

n
r  N r complement
9’s and 10’s Complements

 9’s complement of 674653

• 999999-674653 = 325346
 9’s complement of 023421
• 999999-023421 = 976578
 10’s complement of 674653
• 325346+1 = 325347
 10’s complement of 023421
• 976578+1=976579
1’s and 2’s Complements

 1’s complement of 10111001

• 11111111 – 10111001 = 01000110
• Simply replace 1’s and 0’s
 1’s complement of 10100010
• 01011101
 2’s complement of 10111001
• 01000110 + 1 = 01000111
• Add 1 to 1’s complement
 2’s complement of 10100010
• 01011101 + 1 = 01011110
Subtraction with Complements of Unsigned

 M–N
• Add M to r’s complement of N
 Sum = M+(rn – N) = M – N+ rn
• If M > N, Sum will have an end carry r , discard it
n

• If M<N, Sum will not have an end carry and

 Sum = rn – (N – M) (r’s complement of N – M)
 So M – N = – (r’s complement of Sum)
Subtraction with Complements of Unsigned

 65438 - 5623
65438
10’s complement of 05623 +94377
159815
Discard end carry 105 -100000
Answer 59815
Subtraction with Complements of
Unsigned
 5623 - 65438
05623
10’s complement of 65438 +34562
40185
There is no end carry =>
-(10’s complement of 40185)
-59815
Subtraction with Complements of Unsigned

 10110010 - 10011111
10110010
2’s complement of 10011111 +01100001
100010011
Discard end carry 2^8 -100000000
Answer 000010011
Subtraction with Complements of
Unsigned
 10011111 -10110010
10011111
2’s complement of 10110010 +01001110
11101101
There is no end carry =>
-(2’s complement of 11101101)
Answer = -00010011
Adder

 Design an Adder for 1-bit numbers?

 1. Specification:
2 inputs (X,Y)
2 outputs (C,S)
Adder

 Design an Adder for 1-bit numbers?

 1. Specification:
2 inputs (X,Y)
2 outputs (C,S)
 2. Formulation:

X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Adder

 Design an Adder for 1-bit numbers?

 1. Specification: 3. Optimization/Circuit
2 inputs (X,Y)
2 outputs (C,S)
 2. Formulation:

X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Half Adder

 This adder is called a Half Adder

 Q: Why?

X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Full Adder

 A combinational circuit that adds 3 input bits to generate a Sum bit and a Carry
bit
Full Adder

 A combinational circuit that adds 3 input bits to generate a Sum bit and a Carry
bit

Sum YZ
X Y Z C S
X 00 01 11 10
0 0 0 0 0 0 0 1 0 1 S = X’Y’Z +
0 0 1 0 1 X’YZ’ + XY’Z’
1 1 0 1 0 +XYZ
0 1 0 0 1
Carry =XYZ
0 1 1 1 0
YZ
1 0 0 0 1 X 00 01 11 10
1 0 1 1 0 0 0 0 1 0
1 1 0 1 0 1 0 1 1 1
1 1 1 1 1 C = XY + YZ + XZ
Full Adder = 2 Half Adders

Manipulating the Equations:

S= XY Z
C = XY + XZ + YZ
Full Adder = 2 Half Adders

Manipulating the Equations:

S=(XY)Z
C = XY + XZ + YZ
= XY + XYZ + XY’Z + X’YZ + XYZ
= XY( 1 + Z) + Z(XY’ + X’Y)
= XY + Z(X  Y )
Full Adder = 2 Half Adders

Manipulating the Equations:

S=(XY)Z
C = XY + XZ + YZ = XY + Z(X  Y )

Think of
Z as a
carry in

Src: Mano’s Book

Bigger Adders

• How to build an adder for n-bit numbers?

• Example: 4-Bit Adder
• Inputs ?
• Outputs ?
• What is the size of the truth table?
• How many functions to optimize?
Bigger Adders

• How to build an adder for n-bit numbers?

• Example: 4-Bit Adder
• Inputs ? 9 inputs
• Outputs ? 5 outputs
• What is the size of the truth table? 512 rows!
• How many functions to optimize? 5 functions
Ripple Carry Adder

 To add n-bit numbers:

• Use n Full-Adders in parallel
• The carries propagates as in addition by hand
• Use Z in the circuit as a Cin

 1 0 0 0
 0101
 0110
 1011
Binary Parallel Adder

 To add n-bit numbers:

• Use n Full-Adders in parallel
• The carries propagates as in addition by hand

Src: Mano’s Book

This adder is called ripple carry adder

Subtraction (2’s Complement)

 How to build a subtractor using 2’s complement?

Subtraction (2’s Complement)

 How to build a subtractor using 2’s complement?

Src: Mano’s Book

S = A + ( -B)
Adder/Subtractor

 How to build a circuit that performs both addition and

subtraction?
Adder/Subtractor

0 : Add
1: subtract

Src: Mano’s Book

Using full adders and XOR we can build an Adder/Subtractor!

Binary Parallel Adder (Again)

 To add n-bit numbers:

• Use n Full-Adders in parallel
• The carries propagates as in addition by hand

Src: Mano’s Book

This adder is called ripple carry adder

Multiplexing and Demultiplexing

In some sense, Multiplexing and Demultiplexing is just a

special case of the truth tables we have been studying. You
can look under “multiplexor” and “decoder” in the index of
Tokheim for more information.
Getting Around

 A fair amount of what goes on inside computers or on computer

networks just involves moving data (as opposed to processing that
data).
 Most designs have shared information channels (a bus).
• Part of the path used to get from Point A to Point B may also be along the
way from Point C to Point D.
 Multiplexing and demultiplexing concerns selecting the data to be
transmitted and directing the data to its destination.
Multiplexing

 Multiplexing is sending more than one signal

on a carrier.
 There are two standard types of multiplexing.
• Frequency-Division Multiplexing (FDM): the
medium carries a number of signals, which have
different frequencies; the signals are carried
simultaneously.
• Time-Division Multiplexing (TDM): different
signals are transmitted over the same medium but
they do so at different times – they take turns.
Mutiplexing

Multiplexing allows one to select one of the many possible

sources.
Statistical TDM

 In standard TDM, the inputs take turns, one after

the other gets to put its information onto the wire.
 In Statistical TDM, the input with the most data or
highest priority gets a higher share of the time.
 In this course, our wires hold a single bit of
information at a time, so we will focus on a simple
type of TDM. It will be somewhat more like
statistical TDM in that we will be choosing which
input places its information on the wire.
Multiplexing

 There are several data inputs and one of them is

routed to the output (possibly the shared
communication channel).
• Like selecting a television channel (although that
example is FDM).
 In addition to data inputs, there must be select
inputs.
• The select inputs determine which data input gets
through.
 How many select pins are needed?
• Depends on number of data inputs.
Addresses

 All of the (data) inputs at hand are assigned addresses. The

address of the data input is used to select which data input
is placed on the shared channel.
 So in addition to the collection of data inputs, there are
selection (or address) inputs that pick which of the data
inputs gets through.
How many?

 One bit can have two states and thus distinguish

between two things.
 Two bits can be in four states and …
 Three bits can be in eight states, …
 N bits can be in 2N states
0 0 0 1 0 0
0 0 1 1 0 1
0 1 0 1 1 0
0 1 1 1 1 1
Nomenclature

 A Multiplexer is also known as a MUX.

 A MUX has several data inputs and one data output.
 If the MUX has N (possible) data inputs, it is referred to as an N-
to-1 MUX.
• Since computers work in binary, the N is usually a power of 2.
 An N-to-1 MUX should have log2(N) address inputs (pins).
Log2(N)

N Log2(N) N Log2(N)
2 1 512 9
4 2 1024 10
8 3 2048 11
16 4 4096 12
32 5 8192 13
64 6 16384 14
128 7 32768 15
256 8 65536 16
Combinatorial Logic

 A MUX uses combinatorial logic (as opposed to a

sequential logic which involves memory).
 The output of a MUX depends solely on the data input and
the select input.
 Thus it is just the realization of a truth table.
 Truth table for 2-to-1 MUX

Select Data
When A D0 D1 Out
A=0, 0 0 0 0
Out is 0 0 1 0
same 0 1 0 1
as D0, 0 1 1 1
when
1 0 0 0
A=1,
1 0 1 1
Out is
same 1 1 0 0
as D1 1 1 1 1
Algebra for 2-to-1 MUX

 Take expressions for 1’s found in truth table

 AD0D1 + AD0D1 + AD0D1 + AD0D1
• This can be factored as follows
 AD0(D1+D1) + A(D0+D0)D1
• (D1+D1) = 1
• Not D1 or D1, doesn’t care about D1
• Note that this factoring/reducing requires the two terms to differ by
only one input.
 AD0 + AD1
• (A more general technique for simplifying Boolean expressions uses
the Karnaugh map.)
Karnaugh Version

A B\S 0 1
0 0 0 0
0 1 0 1
1 1 1 1
1 0 1 0
Gates for 2-to-1 MUX

V1
5V

J5

Key = A

U1
NOT

X1
J1
U2
2.5 V
Key = 0 AND2 U4

J2
U3 OR2

Key = 1 AND2
4-to-1 MUX: truth table

Select Data
Out
A B D0 D1 D2 D3
0 0 D0 D1 D2 D3 D0
0 1 D0 D1 D2 D3 D1
1 0 D0 D1 D2 D3 D2
1 1 D0 D1 D2 D3 D3

D0 could be a 1 or a 0, but if A=0 and B=0

then Out is whatever D0 is.
4-to-1 MUX: gate version

V1
5V

J5

Key = A
U1
NOT

J6

Key = B

U2
NOT

J1
U3

Key = 0 AND3
X1
J2
U4

Key = 1
U7
2.5 V
One output
Many inputs
AND3
J3
U5
OR4

Key = 2 AND3
J4
U6

Key = 3 AND3
Addresses

 Each data input is assigned to a specific state of

the select input.
• E.g. low-low, low-high, high-low, high-high
 The state can be interpreted as binary numbers
• 00, 01, 10, 11
• Two select  Four addresses
 And these numbers are thought of as the
“addresses” of the input.
Demultiplexing

 If any of several signals was put onto a single carrier, then at the
other end the signals must be separated and each sent to the
appropriate destination.
 One input (the shared channel) is routed to one of several outputs.
• Like mail, it is possible for me to send a message to any individual one of
you. So there must be a set of paths from me to each of you, and there must
be a mechanism for selecting one of those paths in a particular instance.
 In addition to data input, there must be select inputs.
• To select from 2 N
data outputs requires N select inputs.
Demultiplexing

Demultiplexing allows one to select one of the many possible

destinations.
Nomenclature

 Demultiplexer a.k.a. DeMUX.

 A DeMUX has one data input and several outputs.
• If the DeMUX has N (possible) data outputs, it may
referred to as an 1-to-N DeMUX.
• Since computers work in binary, the N is usually a power
of 2.
• An 1-to-N DeMUX should have log2(N) address inputs
(pins).
• DeMUX are also sometimes referred to by the number of
address pins log2(N)-to-N DeMUX (e.g. 3-to-8 or 2-to-4
DeMUX)
Combinatorial Logic

 A DeMUX has many outputs.

 Each of those outputs depends only on the input data and
the select data (i.e. no memory is involved) .
 Thus a DeMUX is just a realization of a truth table (as is all
combinatorial logic).
1-to-4 DeMux: Truth table

Select Data Output

S1 S0 A O0 O1 O2 O3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1
1-to-4 DeMUX: gate version (may also be
called 2-to-4)
V1
5V

J5

Key = A
U1
NOT

J6

Key = B
U2
NOT

J1 X1
U3

One input Key = 0 AND3

Many outputs
2.5 V

U4 X2

AND3 2.5 V

U5 X3

AND3 2.5 V
U6 X4

AND3 2.5 V
Decoder

 A variation on the previous circuit is to have

no input data.
 The selected output will be high, the others
low.
• Or vice versa.
 This can be used to activate a control pin on
the selected part of circuit.
 2 to 1 Line Encoder

 Schematic & Truth Table

 Simplest line encoder is 2 to 1 line encoder in which
there are 2 input lines and 1 output line. 2 to 1 line
Encoder schematic and truth table are given below.
Decoding

 Decoding - the
• Conversion of n-bit input to m-bit output
• Given n £ m £ 2 n

 Circuits that perform decoding are called

decoders
• Called n-to-m line decoders, where m £ 2 , and
n

• Generate 2 (or fewer) minterms for the n input

n

variables
Decoder Examples

 1-to-2-Line Decoder A D0 D1
D0 5 A
0 1 0
1 0 1 A D1 5 A
 2-to-4-Line Decoder (a) (b)
A0
A1 A0 D 0 D1 D2 D3
A1
0 0 1 0 0 0 D0 5 A 1 A 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1 D1 5 A 1 A 0

(a)
D2 5 A 1 A 0
 Note that the 2-4-line
made up of 2 1-to-2- D3 5 A 1 A 0

line decoders and 4 AND gates. (b)

 Decoder Expansion - Example

 Result 4 2-input ANDs 8 2-input ANDs

D0
A0

D1

A1
D2

2-to-4-Line D3
decoder
D4

A2 D5

1-to-2-Line decoders D6

D7

3-to-8 Line decoder

Decoder with Enable

 In general, attach m-enabling circuits to the outputs

 See truth table below for function
• Note use of X’s to denote both 0 and 1
• Combination containing two X’s represent four binary combinations
 Alternatively, can be viewed as distributing value of signal EN to
1 of 4 outputs EN
A
 In this case, called a 1

A
demultiplexer 0
D 0

EN A 1 A 0 D0 D1 D2 D3 D1

0 X X 0 0 0 0
1 0 0 1 0 0 0 D2
1 0 1 0 1 0 0
1 1 0 0 0 1 0
D3
1 1 1 0 0 0

(b)
The circuit functionality of a 1 bit ALU is shown here,
depending upon the control signal S1 and S0 the circuit operates
as follows:

for Control signal S1 = 0 , S0 = 0, the output is A And B,

for Control signal S1 = 0 , S0 = 1, the output is A Or B,

for Control signal S1 = 1 , S0 = 0, the output is A Xor B,

for Control signal S1 = 1 , S0 = 1, the output is A Add B.

SEQUENTIAL LOGIC
CIRCUITS

Flip=Flo
p

Latch
Latches and Flip-flops

Bi-stable circuit (no inputs)

How do we store info? Feedback

 Two inverters can hold a bit

• As long as power is applied
"1"

"0" "stored bit"

Storing a new memory

• Temporarily break the feedback path
"remember"

"load"
"data" "stored bit"
LATCH

Set Reset
Two Type
(SR)

Set (S) input

: HIGH or 1
NAND
state Gate Latch

Reset (R)
input : LOW
NOR Gate
or 0 state Latch
NAND GATE LATCH
 Flip-flops
Latches
 A latch is a temporary storage device that has two stable states
(bistable). It is a basic form of memory.

The S-R (Set-Reset) latch is the most basic type. It can be constructed
from NOR gates or NAND gates. With NOR gates, the latch responds to
active-HIGH inputs; with NAND gates, it responds to active-LOW inputs.

NOR Active-HIGH Latch NAND Active-LOW Latch

SR Latch
 Flip-flops
 A device that stores either a 0 or 1.
 Stored value can be changed only at certain times determined by a
clock input.
 New value depend on the current state and it’s control inputs
 A digital circuit that contains flip-flops is called a sequential
circuit

S-R flip-flops D flip-flop J-K flip-flops T flip-flop

 Flip-flops

Flip-flop :is a clocked device, in which only the clock edge

determines when a new bit is entered.
Flip-flop differs from a latch in the manner it changes states.

The active edge can be positive or negative.

Gated SR latch timing diagram

OR
 Latches
A gated latch is a variation on the basic latch.
The gated latch has an additional input, called enable (Clk) that must be
HIGH in order for the latch to respond to the S and R inputs.

Show the Q output with relation to the input

signals. Assume Q starts LOW.

Keep in mind that S and R are only active when Clk is HIGH.
 D Latches
The D latch is an variation of the S-R latch but combines the S
and R inputs into a single D input as shown:

A simple rule for the D latch is: Q follows D when the Enable is active.
Asynchronous (Ripple) Counters

 Example: 2-bit ripple binary counter.

 Output of one flip-flop is connected to the clock input of
the next more-significant flip-flop.
HIGH

J Q0 J Q1
CLK C C
Q0
K K

FF0 FF1

CLK 1 2 3 4

Q0 Timing diagram
00  01  10  11  00 ...
Q0 0 1 0 1 0

Q1 0 0 1 1 0
Asynchronous (Ripple) Counters

 Example: 3-bit ripple binary counter.

HIGH

J Q0 J Q1 J Q2
CLK C Q0 C Q1 C
K K K
FF0 FF1 FF2

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

Q2 0 0 0 0 1 1 1 1 0

Recycles back to 0
 Registers
 Register – a collection of binary storage elements
 In theory, a register is sequential logic, i.e. can be defined by a state
table
 But more often, we think of a register as an array of n flip flops
(possibly with some extra gates) that store a vector of n binary bits
 Used to perform simple data storage, movement, manipulation and
processing operations (e.g. load, increment, shift, add, etc.)
 The computer processes data by performing operations on
registers, e.g. ADD A, B where A and B are say 32-bit registers

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