GROUP 6

MEMBERS;
ADRIANE ISIDORE S. MONTEZA IAN JAMES LABARCON
PHIL ALBERT C. ESTOPIL JAKE AERON HABASA
BOB DOMINIC E. PUERTO
ANDREW P. AMANDURON
3.2 RECOGNIZE CLOCK
GENERATOR CIRCUITS
CLOCKS AND TIMING SIGNALS
Most sequential logic circuits are driven by a
clock oscillator. This usually consists of an
astable circuit producing regular pulses that
should ideally:

1. Be constant in frequency
Clock oscillators use crystals for stable frequency. High
frequencies are reduced to lower ones using counters.

2.Have fast rising and falling edges to its pulses

Quick rising and falling edges (under 100ns) ensure accurate
timing. Buffers are used to maintain signal quality when driving
multiple gates.
3. Have the correct logic levels. The signals produced by the clock
circuits must have appropriate the logic levels for the circuits being
supplied.

4.Simple clock oscillator

Fig. 5.1.1 shows a simple oscillator with three components,
using a Schmitt inverter. The inverter switches states quickly
and has different input levels (Vt+ and Vt−) for changing
from 0 to 1 and 1 to 0.

Here’s how it works:

1. If the input is 0, the output becomes 1, and the capacitor

(C) charges through the resistor (R).
2. When the input reaches Vt+, the output switches to 0,
and C discharges through R.
3. Once the input drops to Vt−, the cycle repeats.

This creates a pulse waveform with fast rise and fall times
and a mark-to-space ratio of about 1:3.
5.Crystal controlled clock oscillator Fig. 5.1.3
shows a crystal oscillator using three gates
from a 74HCT04 IC to produce a stable
3.276MHz frequency. The frequency can be
lowered by dividing it through flip-flops.

Fig. 5.1.4 illustrates the process, where the

original clock signal is divided by 4 using two
flip-flops. This reduces the frequency and
transforms the waveform into a square shape
with a 1:1 mark-to-space ratio.
6.Two phase clock signals Older microprocessor systems used two-
phase clock signals. With a source clock running at twice the required
frequency, the microprocessor could perform two actions per cycle,
improving efficiency and saving processing time.

7.Producing a two phase clock signal A

clock signal with a 1:1 mark-to-space
ratio can produce two non-overlapping
clock pulses, often called ϕ1 and ϕ2, as
shown in Fig. 5.1.5. This is done by
feeding the clock signal into a JK flip-flop
in toggle mode, with both J and K set to
logic 1.
8.Distributing Clock Signals Specialized clock oscillator ICs are designed for
applications like computers, wireless communication, and medical devices.

9.Clock Fan-Out Clock signals must drive multiple ICs without losing accuracy, speed,
or amplitude. Fast rise and fall times should be maintained, but this can cause issues
like waveform ringing. A square wave shape is ideal.

10.Circuit Capacitance The capacitance from multiple gates can slow clock signals. To
counter this, low-impedance clock buffers or Schmitt triggers restore the signal and
ensure a large fan-out.

11.Cross-Talk In large circuits, noise and cross-talk may cause skew errors, where
clock signals arrive at different times. Miniaturization and technologies like ECL or
LVDS with differential outputs can reduce interference. Application-specific ICs (ASICs)
are commonly used for high-frequency clock distribution.
3.3 DIFFERENTIATE THE KINDS OF
FLIP FLOPS
1. SR flip-flop
is a set-reset flip-flop controlled by a clock. The state of the flip-flop changes
only on the rising edge of the clock pulse. S (Set): Makes the output HIGH. R
(Reset): Makes the output LOW. If both S and R are HIGH at the same time,
the output becomes uncertain.
Inputs: S (Set), R (Reset) - Operation: - S=0, R=0: No change in output. -
S=1, R=0: Sets the output Q to 1. - S=0, R=1: Resets the output Q to 0. -
S=1, R=1: Undefined/forbidden state; output is unpredictable. - Limitations:
The undefined state (S=1, R=1) is a significant drawback.
2.JK flip-flop
Named after Jack Kilby, is a sequential logic circuit created in the 1950s at
Texas Instruments. It is used to store and process binary data in digital
systems.
Inputs: J (Set), K (Reset) - Operation: Similar to SR, but the J=1, K=1 state is
defined: it toggles the output (Q changes state). - Advantages: Eliminates the
undefined state of the SR flip-flop. More versatile than SR.
3.D (or Delay) Flip Flop
is a digital electronic circuit used to delay the change of state of its output
signal (Q) until the next rising edge of a clock timing input signal occurs.
Input: D (delay) - Operation: The output Q directly follows the input D after
a clock pulse. It's a simple data latch. - Advantages: Simple and
predictable behavior, making it easier to design and use in sequential
circuits.

4. T flip-flop
is a single-input circuit that toggles its output, meaning it switches the
output to the opposite state with each clock pulse. "T" stands for Toggle.
Input: T (Toggle) - Operation: When T=1, the output Q toggles (changes
state) on each clock pulse. When T=0, the output remains unchanged. -
Advantages: Useful for applications requiring simple counting or
frequency division.
3.4 DIFFERENTIATE THE KINDS OF ASYNCHRONOUS AND
SYNCHRONOUS COUNTERS
There are two types of counters in digital logic circuit that are used to count the
numbers of bits and these types depends upon the clock pulse applied to the flip
flops.
1. Asynchronous Counter: These are the counters in which we do not use universal
clock, main clock is only applied to the first flip flop and then for rest of flip flops the
output of previous flip flop is taken as a clock.
2. Synchronous Counter: These are the counters in which we use a
universal clock that is common to all flip flops. The Circuit diagram of
Synchronous Counter is given Below:
 DIFFERENCE TABLE
SYNCHRONOUS COUNTERS ASYNCHRONOUS COUNTERS

In synchronous counter we use a universal clock that is In asynchronous counter main clock is only applied to
common to all flip flops through out the circuit. the first flip flop and then for rest of flip flops the
output of previous flip flop is taken as a clock.
.Synchronous Counter is faster in operation as Asynchronous Counter is slower as compared to
compared to Asynchronous Counter. synchronous counter in operation.
Synchronous Counter does not produce any decoding Asynchronous Counter produces decoding error.
errors.
Synchronous Counter is also called Parallel Counter. Asynchronous Counter is also called Serial Counter.

Synchronous Counter designing as well implementation Asynchronous Counter designing as well as

are complex due to increasing the number of states. implementation is very easy.
3.5 USE AVAILABLE SOFTWARE TO
SIMULATE COUNTER OPERATION
1. Circuit Construction Kit: Ideal for beginners, it helps
users build simple circuits with basic components
like bulbs and switches while monitoring with
voltmeters and ammeters.

2. CircuitLogicx: Windows-based software with 4,000+

components (12,000 in the pro version), perfect for
beginners progressing to advanced designs.

3. CircuitMod: Minimalist interface for designing and

simulating complex circuits in real-time, saving
projects in CMF format for editing. Deeds: Advanced
Windows simulator for digital circuits, featuring
hardware like ALUs, decoders, and memory devices.
4. LT Spice Simulator: Versatile tool by Linear
Technology with access to 200+ models, suited
for Linear Technology parts users.

5. Micro-Cap: Windows-based simulator with a

user-friendly interface, offering extensive tools
in its paid version.

6. Proteus: Mixed-mode simulation tool with

real-time circuit and PCB design, widely used in
education.
7. QUCS: Open-source tool for almost any circuit
design, modifiable for advanced programmers.

8. Tina-TI: User-friendly with extensive component

libraries, providing detailed error and simulation
analysis.

9. SPICE: Advanced simulation for analog and digital

circuits, popular in academic research for complex
tests.

10. 123D Circuits: AutoDesk’s detailed PCB design

tool with 3D-rendered components for real-time
interaction.
THANK YOU!
[email protected]