Scribd
Upload
17 views

Lecture9 Fall24

Uploaded by

rashidhussain76340
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
17 views

Lecture9 Fall24

Uploaded by

rashidhussain76340
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 31

Lecture # 9

sequential circuit designing and analysis/state table and diagram

By: Muhammad Zain Uddin


email: [email protected]

M. ZAIN UDDIN 1
Sequential Circuit Analysis
DIGITAL LOGIC DESIGN
Presentation Outline
Analysis of Clocked Sequential circuits

◦ State and Output Equations

◦ State Table

◦ State Diagram

Mealy versus Moore Sequential Circuits

◦ State and Timing Diagrams


Analysis of Clocked Sequential
Circuits
Analysis is describing what a given circuit will do

The output of a clocked sequential circuit is determined by

1. Inputs

2. State of the Flip-Flops

Analysis Procedure:

3. Obtain the equations at the inputs of the Flip-Flops

4. Obtain the output equations

5. Fill the state table for all possible input and state values

6. Draw the state diagram


Analysis Example
Is this a clocked sequential circuit?
YES!
What type of Memory?
D Flip-Flops
How many state variables?
Two state variables: and
What are the Inputs?
One Input:
What are the Outputs?
One Output:
Flip-Flop Input Equations
What are the equations on the inputs of the
flip-flops?

and are the current state

and are the next state

The values of and will be

and at the next clock edge


Next State and Output
Equations
The next state equations define
the next state

At the inputs of the Flip-Flops

Next state equations?

There is only one output

What is the output equation?


State Table
State table shows the Next State and Output in a tabular form

Next State Equations: and

Output Equation:

Another form of the state table


State Diagram
State diagram is a graphical representation of a state table
The circles are the states
Two state variable  Four states (ALL values of and )
Arcs are the state transitions
Labeled with: Input / Output
Combinational versus Sequential
Analysis
Analysis of Combinational Circuits Output is a function of
Obtain the Boolean Equations input only

Fill the Truth Table

Analysis of Sequential Circuits


Next state is a function of
Obtain the Next State Equations input and current state
Obtain the Output Equations
Output is a function of
Fill the State Table input and current state
Draw the State Diagram
Example with Output = Current
State
Analyze the sequential circuit shown below
Two inputs: and
One state variable
No separate output  Output = current state
Obtain the next state equation, state table, and state diagram
Example with Output = Current
State

Flip-Flop Input Equation:

⨁ ⨁

Next State Equation: ⨁ ⨁


Sequential Circuit with T Flip-
Flops
Circuit has two T Flip-Flops
One Input
One output
Two state variables: and
Obtain the T-FF input equations
Obtain the next state equations
Fill the state table
Draw the state diagram
Recall: Flip-Flop Characteristic
Equation
For D Flip-Flop:
These equations define
For T Flip-Flop: ⨁
the Next State
For JK Flip-Flop:

D Flip-Flop T Flip-Flop JK Flip-Flop


D Q(t+1) T Q(t+1) J K Q(t+1)
0 0 Reset 0 Q(t) No change 0 0 Q(t) No change
1 1 Set 1 Q'(t) Complement 0 1 0 Reset
1 0 1 Set
1 1 Q'(t) Complement
Sequential Circuit with T Flip-
Flops
T Flip-Flop Input Equations:

Next State Equations:


⨁ ⨁
⨁ ⨁
Output Equation:
From Next State Equations to
State Table
T Flip-Flop Input Equations:

Next State Equations:

Output Equation: Notice that the output is a function of


the present state only.
It does NOT depend on the input
From State Table to State
Diagram

Four States: (drawn as circles)


Output Equation: (does not depend on input )
Output is shown inside the state circle ()
Sequential Circuit with a JK Flip-
Flops
One Input and two state variables:
and (outputs of Flip-Flops)

No separate output  Output =


Current state

Obtain the JK input equations

Obtain the next state equations

Fill the state table

Draw the state diagram


JK Input and Next State
Equations
JK Flip-Flop Input Equations:
and
and ⨁

Next State Equations:

Substituting:
From JK Input Equations to State
Table
JK Input Equations: , , and ⨁
From State Table to State
Diagram
Four states: (drawn as circles)
Arcs show the input value on the state transition
Mealy versus Moore Sequential
Circuits
There are two ways to design a clocked sequential circuit:
1. Mealy Machine: Outputs depend on present state and inputs
2. Moore Machine: Outputs depend on present state only
Mealy Machine
The outputs are a function of the present state and Inputs

The outputs are NOT synchronized with the clock

The outputs may change if inputs change during the clock cycle

The outputs may have momentary false values (called glitches)

The correct outputs are present just before the edge of the clock
Mealy State Diagram
An example of a Mealy state diagram is shown on the
right

Each arc is labeled with:


Input / Output

The output is shown on the arcs of the state diagram

The output depends on the current state and input

Notice that State 11 cannot be reached from the other


states
Tracing a Mealy State Diagram
Cycle 0 1 2 3 4 5 6 7 8

Input x 0 1 1 0 1 1 1 1 0

Present ? 0 0 1 0 0 1 1 1
State A B ? 0 1 0 0 1 0 0 0

Output z 0 0 0 0 0 0 1 1 0

 When the circuit is powered, the initial state (AB) is unknown

 Even though the initial state is unknown, the input x = 0 forces a transition to
state AB = 00, regardless of the present state
 Sometimes, a reset input is used to initialize the state to 00
False Output in the Timing
Diagram
Cycle 0 1 2 3 4 5 6 7 8
Input x 0 1 1 0 1 1 1 1 0
Present ? 0 0 1 0 0 1 1 1
State A B ? 0 1 0 0 1 0 0 0
Output z 0 0 0 0 0 0 1 1 0

Negative edge-triggered
A

B
Moore Machine
The outputs are a function of the Flip-Flop outputs only

The outputs depend on the current state only

The outputs are synchronized with the clock

Glitches cannot appear in the outputs (even if inputs change)

A given design might mix between Mealy and Moore


Moore State Diagram 0
An example of a Moore state diagram is
0
shown on the right
00 1 01
0 0
Arcs are labeled with input only

The output is shown inside the state: (State 0 0 1


/ Output)
11 10
The output depends on the current state 1 1 0
only
1
Tracing a Moore State Diagram 0

When the circuit is powered, the initial state 0


(AB) and output are unknown 00 1 01
Input x = 0 resets the state AB to 00. Can also 0 0
be done with a reset signal.

Cycle 0 1 2 3 4 5 6 7 8 0 0 1

Input x 0 1 1 0 1 1 1 1 0
11 10
Present ? 0 0 1 0 0 1 1 1 1 1 0
State A B ? 0 1 0 0 1 0 1 1
Output z ? 0 0 0 0 0 0 1 1 1
Timing Diagram of a Moore
Machine
Cycle 0 1 2 3 4 5 6 7 8
The output is
Input x 0 1 1 0 1 1 1 1 0
synchronized with the
Present ? 0 0 1 0 0 1 1 1
State A B clock. No false output
? 0 1 0 0 1 0 1 1
Output z ? 0 0 0 0 0 0 1 1 (or glitch) can appear.

Negative edge-triggered
A

B
Summary
To analyze a clocked sequential circuit:
1. Obtain the equations at the Inputs of the flip-flops
2. Obtain the Next State equations
◦ For a D Flip-Flop, the Next State = D input equation
◦ For T and JK, use the characteristic equation of the Flip-Flop

3. Obtain the Output equations


4. Fill the State Table
◦ Put all the combinations of current state and input
◦ Fill the next state and output columns

5. Draw the State Diagram


Two types of clocked sequential circuits: Mealy versus Moore

You might also like