Number Representation and their

Operations
Numbers can be represented in 3 formats:
i. Signed magnitude
ii. 1's complement
iii. 2's complement
• In all three formats, MSB=0 for +ve numbers & MSB=1 for -ve
numbers.
• In signed magnitude system, negative value is obtained by
changing the MSB from 0 to 1 of the corresponding positive value.
For ex, +5 is represented by 0101 & -5 is represented by 1101.
• In 1's complement system, negative values are obtained by
complementing each bit of the corresponding positive number.
For ex, -5 is obtained by complementing each bit in 0101 to yield
1010.
• In 2's complement system, the 2's complement of a number is
obtained by adding 1 to the 1's complement of that number. For
ex, -5 is obtained by complementing each bit in 0101 & then
adding 1 to yield 1011.
Addition and Subtraction of Signed
Magnitude Data
• We designate the magnitude of the two numbers by A and B.
• When the signed numbers are added or subtracted, we find that there
are eight different conditions to consider, depending on the sign of the
numbers and the operation performed.
• These conditions are listed in the first column of Table.
• The algorithms for addition and subtraction are derived from the table.
Addition (subtraction) algorithm

Addition (subtraction) algorithm:

• when the signs of A and B are identical , add the two magnitudes
and attach the sign of A to the result.
• When the signs of A and B are different , compare the magnitudes
and subtract the smaller number from the larger.
• Choose the sign of the result to be the same as A if A B or the
complement of the sign of A if A B.
• If the two magnitudes are equal, subtract B from A and make the
sign of the result positive.
Rules for Addition And
Subtraction using Signed
Magnitude
1. When the signs of A and B are same, add the two magnitudes
and attach the sign of result is that of A.
2. When the signs of A and B are not same, compare the
magnitudes and subtract the smaller number from the larger.
And give the sign of larger magnitude to the result.
3. If the two magnitudes are equal, subtract B from A and make
the sign of the result will be positive.
Hardware for signed-magnitude
addition and subtraction
• Let A and B be two registers that hold the magnitudes of the
numbers
• A and B, be two flip-flops, which hold the corresponding signs
• Parallel adder is needed to perform the micro0operation A + B
• The Complementer for generating the 2's Complement while
performing subtraction operation
Hardware Implementation
• It consists of registers A and B and sign flip-flops A and B,
subtraction is done by adding A to the 2's complement of B. S
• The output carry is transferred to flip flop E, where it can be
checked to determine the relative magnitudes of the two numbers.
• The add-overflow flip-flop AVF holds the overflow bit when A
and B are added.
• The addition of A plus B is done through the parallel adder. The
S(sum) output of the adder is applied to the input of the A register.
The complementer provides an output of B or the complement of
B depending on the state of the mode control M.
• The M signal is also applied to the input carry of the adder. When
M = 0 the output of B is transferred to the adder, the input carry is
0, and the output of the adder is equal to the sum A + B.
• When M = 1 the 1's complement of B is applied to the adder, the
input carry is 1, and output S = A + B' + 1
Flowchart for Add and Subtract
Operation
Flowchart for add and subtract operations
• The two signs A, and B, are compared by an XOR gate. If the
output of the gate is 0, the signs are identical; if it is 1, the signs
are different.
• For an add operation, identical signs dictate that the magnitudes
be added.
• For a subtract operation, different signs dictate that the
magnitudes be added.
• The magnitudes are added with a microoperation EA- A+B,
where EA is a register that combines E and A. The carry in E after
the addition constitutes an overflow if it is equal to 1. the value of
E is transferred into the add-overflow flip flop AVF.
• The two magnitudes are subtracted if the signs are different for an
add operation or identical for a subtract operation.
• The magnitudes are subtracted by adding A to the 2's complement
of B. No overflow can occur if the numbers are subtracted to AVF
is cleared to 0. A 1 in E, indicates that A > B and the number in A
is the correct result.
• If this number is zero, the sign A, must be made positive to avoid
a negative zero. A 0 in E indicates that A < B.
Example:

• (8) + (- 3) = 5
• (- 8) + (- 3) = - 11
• (8) - (- 3) = 11
• (- 8) - (- 3) = - 5
Addition and subtraction with Signed- 2's
Complement Data
Hardware for signed-2's Complement
addition and subtraction
Hardware for signed-2's Complement
addition and subtraction

• AC and BR are the registers to hold the numbers.

• The leftmost bit in AC and BR represent the sign bits of the
numbers.
• The two sign bits are added or subtract together with the other
bits in t complementer and parallel adder.
• The overflow flip flop V is set to 1 if there is overflow.
Algorithms:
• The sum is obtained by adding the contents of AC and BR.
• The overflow bit V is set to 1 if the exclusive OR of the last two
carries is 1, and it is cleared to 0 otherwise.
• The subtraction operation is accomplished by adding the content
of AC to the 2's complement of BR. Taking the 2's complement of
BR has the effect of changing a positive number to negative, and
vice versa.
Rules for addition using 2's complement

When two negative numbers are added a carry will be generated

from the sign bit which will be discarded. 2's complement of the
magnitude bits of the operation will be the final sum.
Rules for subtraction using 2's complement

i. At first, 2's complement of the negative number is found.

ii. Then it is added to the other number.
iii. If the final carry over of the sum is 1, it is dropped and the
result is positive.
iv. If there is no carry over, the two's complement of the sum will
be the result and it is negative.
How to calculate binary value of negative
number

Example: (-3)
First find the binary value of (+ 3) then find the 2's complement.
+3 = 0011
2's complement =1100 +1= 1101
-3 =1101
 Multiplication Algorithm in Signed Magnitude

Multiplication of two fixed point binary number in signed

magnitude representation is done with process of successive
shift and add operation.
In the multiplication process we are considering successive bits of
the multiplier, least significant bit first.
If the multiplier bit is 1, the multiplicand is copied down else 0’s
are copied down.

The numbers copied down in successive lines are shifted one

position to the left from the previous number.
Finally numbers are added and their sum form the product.

The sign of the product is determined from the sign of the

multiplicand and multiplier. If they are alike, sign of the product is
positive else negative.
Hardware Implementation :
1. Registers:
Two Registers B and Q are used to store multiplicand and
multiplier respectively.
Register A is used to store partial product during multiplication.
Sequence Counter register (SC) is used to store number of bits
in the multiplier.

2. Flip Flop:
To store sign bit of registers we require three flip flops (A sign,
B sign and Q sign).
Flip flop E is used to store carry bit generated during partial
product addition.
3. Complement and Parallel adder:
This hardware unit is used in calculating partial product i.e,
perform addition required.
Flowchart of Multiplication:
1. Initially multiplicand is stored in B register and multiplier is
stored in Q register.
2. Sign of registers B (Bs) and Q (Qs) are compared
using XOR functionality (i.e., if both the signs are alike, output
of XOR operation is 0 unless 1) and output stored in As (sign of
A register).Note: Initially 0 is assigned to register A and E flip
flop. Sequence counter is initialized with value n, n is the
number of bits in the Multiplier.
3. Now least significant bit of multiplier is checked. If it is 1 add
the content of register A with Multiplicand (register B) and
result is assigned in A register with carry bit in flip flop E.
Content of E A Q is shifted to right by one position, i.e., content
of E is shifted to most significant bit (MSB) of A and least
significant bit of A is shifted to most significant bit of Q.
4. If Qn = 0, only shift right operation on content of E A Q is
performed in a similar fashion.
5. Content of Sequence counter is decremented by 1.
6. Check the content of Sequence counter (SC), if it is 0, end the
process and the final product is present in register A and Q, else
repeat the process.
Example:
Multiplicand – 10111
Multiplier - 10011
Booth’s Algorithm of Multiplication

Booth algorithm gives a procedure for multiplying binary integers

in signed 2’s complement representation in efficient way, i.e., less
number of additions/subtractions required. It operates on the fact
that strings of 0’s in the multiplier require no addition but just
shifting and a string of 1’s in the multiplier from bit weight 2^k to
weight 2^m can be treated as 2^(k+1 ) to 2^m.
As in all multiplication schemes, booth algorithm requires
examination of the multiplier bits and shifting of the partial
product.
Prior to the shifting, the multiplicand may be added to the partial
product, subtracted from the partial product, or left unchanged
according to following rules:

1. The multiplicand is subtracted from the partial product upon

encountering the first least significant 1 in a string of 1’s in the
multiplier
2. The multiplicand is added to the partial product upon
encountering the first 0 (provided that there was a previous ‘1’)
in a string of 0’s in the multiplier.
3. The partial product does not change when the multiplier bit is
identical to the previous multiplier bit.
Hardware Implementation of Booths Algorithm – The hardware
implementation of the booth algorithm requires the register
configuration shown in the figure below.
We name the register as A, B and Q, AC, BR and QR respectively.
Qn designates the least significant bit of multiplier in the register
QR. An extra flip-flop Qn+1is appended to QR to facilitate a
double inspection of the multiplier. The flowchart for the booth
algorithm is shown below.
AC and the appended bit Qn+1 are initially cleared to 0 and the
sequence SC is set to a number n equal to the number of bits in the
multiplier. The two bits of the multiplier in Qn and Qn+1are
inspected. If the two bits are equal to 10, it means
that the first 1 in a string has been encountered. This requires
subtraction of the multiplicand from the partial product in AC. If
the 2 bits are equal to 01, it means that the first 0 in a string of 0’s
has been encountered. This requires the addition of the
multiplicand to the partial product in AC.
When the two bits are equal, the partial product does not change.
An overflow cannot occur because the addition and subtraction of
the multiplicand follow each other. As a consequence, the 2
numbers that are added always have a opposite signs, a condition
that excludes an overflow. The next step is to shift right the partial
product and the multiplier (including Qn+1). This is an arithmetic
shift right (ashr) operation which AC and QR ti the right and leaves
the sign bit in AC unchanged. The sequence counter is decremented
and the computational loop is repeated n times.
Division Algorithms (Integer Division)

Division of two fixed-point binary numbers in signed-magnitude

representation is done with paper and pencil by a process of
successive compare, shift, and subtract operations. Binary division
is simpler than decimal division because the quotient digits are
either 0 or 1 and there is no need to estimate how many times the
dividend or partial remainder fits into the divisor.
Hardware Implementation for Signed-
Magnitude Data

When the division is implemented in a digital computer, it is

convenient to change the process slightly. Instead of shifting the
divisor to the right, the dividend, or partial remainder, is shifted to
the left, thus leaving the two numbers in the required relative
position. Subtraction may be achieved by adding A to the 2’s
complement of B. The information about the relative magnitudes is
then available from the end-carry.
 Hardware Algorithm

The hardware divide algorithm is shown in the flowchart of Fig. 10-13.

The dividend is in A and Q and the divisor in B. The sign of the result is
transferred into Q s to be part of the quotient. A constant is set into the
sequence counter SC to specify the number of bits in the quotient. As in
multiplication, we assume that operands are transferred to registers from a
memory unit that has words of n bits. Since an operand must be stored
with its sign, one bit of the word will be occupied by the sign and the
magnitude will consist of n 1 bits. A divide-overflow condition is tested
by subtracting the divisor in B from half of the bits of the dividend stored
in A. If A B, the divide-overflow flip-flop DVF is set and the operation is
terminated prematurely. If A B, no divide overflow occurs so the value of
the dividend is restored by adding B to A.
1. Initially, the dividend is in A & Q and the divisor is in B.
2. The sign of the result is transferred into Q, to be part of the
quotient. Then a constant is set into the SC to specify the
number of bits in the quotient.
3. Since an operand must be saved with its sign, one bit of the
word will be inhabited by the sign, and the magnitude will be
composed of n -1 bits.
4. The condition of divide-overflow is checked by subtracting the
divisor in B from the half of the bits of the dividend stored in A.
If A ≥ B, DVF is set and the operation is terminated before
time. If A < B, no overflow condition occurs and so the value
of the dividend is reinstated by adding B to A.
5. The division of the magnitudes starts with the dividend in AQ to
left in the high-order bit shifted into E.
(Note – If shifted a bit into E is equal to 1, and we know that
EA > B as EA comprises a 1 followed by n -1 bits whereas B
comprises only n -1 bits). In this case, B must be subtracted
from EA, and 1 should insert into Q, for the quotient bit.
6. If the shift-left operation (shl) inserts a 0 into E, the divisor is
subtracted by adding its 2’s complement value and the carry is
moved into E. If E = 1, it means that A ≥ B; thus, Q, is set to 1.
If E = 0, it means that A < B, and the original number is
reimposed by adding B into A.
7. Now, this process is repeated with register A containing the
partial remainder.