Input – Output Organization

Chapter 7
 Introduction
Data transfer between the computer and external device take
place through I/O mechanism. One communicates with a
computer system via the I/O devices interfaced to it. The
user can enter programs and data using keyboard on a
terminal, executes the programs to obtain results and finally
the results may be displayed on monitor of the computer.
Therefore, the I/O devices connected to a computer system
provide an efficient means of communication between the
computer and the outside world. These I/O devices are
commonly known as peripherals and popular I/O devices
used are keyboard, monitor, printer, disk and mouse.
Every computer supports a variety of peripheral
devices. To use a peripheral device, two modules are
required :

I. I/O interface or I/O controller.

II. I/O driver.
 I/O Interface or I/O Controller
I/O interface is a hardware device provides a means for transferring
information between central system(i.e. CPU and main memory) and
external I/O peripheral device. Peripheral devices connected to a
computer need I/O interface circuits for interfacing then with the CPU
and/or memory. Each peripheral has its own I/O controller that operates
the particular device. The purpose of the I/O interface is to resolve the
differences that exist between the central computer and each peripheral.
The major differences are :
• Peripherals are mainly electromechanical and electromagnetic
devices
and their manner of operations is different from the operation of the

CPU and main memory, which are electronic devices. Hence, a

conversion of signal values may be required.
• Data codes and formats in peripheral devices are different from the
code format in the CPU and memory.
• The data transfer rate of the peripheral devices is usually slower than

the transfer rate of the CPU and therefore, a synchronization

mechanism may be required.
• The various peripheral devices attached to a computer have different
modes of operations and each must be controlled so as not disturb
the
operation of other peripherals connected to the CPU.
 Connection of I/O bus to I/O
controllers
Main
Memory

Address lines
CPU Data lines
Control lines

Keyboar
Printer Disk Monitor
d
Controll Interfac Controll
Interfac
er e er
e

Magneti
Keyboar
Printer c Monitor
d
Disk
 Cont…
There are four types of I/O commands that an I/O interface may
received when it is addressed by the processor :
1. Control : It is used to enable an I/O device and to give directive
what
to do.
2. Test : It is used to test various status conditions associated with an
I/O interface and its peripheral. Ex. Power on state, ready
state etc.
3. Read : This causes the I/O interface to obtain a data – item from
the
peripheral and places it in an internal buffer.
4. Write : This causes the I/O interface to take a data – item from the
data bus and subsequently transfers that to the
peripheral.
Examples of I/O Interfaces :
 SCSI (Small Computer System Interface)
 USB (Universal Serial Bus)
 IDE ( Integrated Drive Electronics)
 Centronics Interface
 FireWire etc.
 I/O Driver
I/O driver is a software module that issues different commands to
the I/O controller, for executing various I/O operations. Following
are certain operations performed by different I/O drivers :
 Reading a file from disk.
 Printing some lines by the printer.
 Displaying a message on monitor.
 Storing some data on disk.
The I/O driver program for a given peripheral device is developed
only after knowing the architecture of the I/O controller device.
The I/O driver program and I/O controller device together achieve
the I/O operation done on behalf of corresponding peripheral
device. An I/O operation can be performed by calling the relevant
I/O interface ( or I/O controller) and passing relevant signals for
operation. After completing the I/O operation, the I/O driver
returns control to the called program and pass return signals
about the completion of the operation. The collection of I/O driver
programs is called BIOS (Basic Input Output System) which is
physically stored in ROM part of main memory. Some I/O drivers
are also installed in the hard disk which are brought into the RAM
by bootstrap system program during booting. The communication
between I/O controller and application program is shown in the
next slide.
 communication between I/O
controller and application program

Applicati Program Call Command I/O

BIO
on OS controll
S
Program Result Return Status er

I/O Device
 Accessing I/O Devices
Like the I/O bus, the memory bus contains data, address and
read/write control lines. In addition to communicating with I/O,
the processor must communicate with the memory unit. There
are three ways that processor uses computer buses to
communicate with memory and I/O :
1. Use two separate busses (address, data and control), one for
memory
and other for I/O.
2. Use one common bus (address and data) for both memory and
I/O but have separate control lines for each.
3. Use one common bus (address, data and control) for memory
and I/O.

In the first case, the computer has separate sets of data, address,
and control buses, one for accessing memory and the other
for I/O. This procedure is used in computers that provide a
separate I/O processor (IOP), also called I/O channel in
addition to the CPU. The memory communicates with both the
CPU and the IOP through a memory bus The objective of the
IOP is to provide a separate path for the transfer of
information between external I/O devices and internal
 Common Address and Data bus but
separate Control bus
In this case, computers use one common bus to transfer
information between memory or I/O and the CPU. The
distinction between a memory transfer and I/O transfer is
made through separate read and write lines. The CPU
specifies whether the address on the address lines is for a
memory word or for an interface register by enabling one of
two possible read or write lines. I/O – read and I/O – write
control lines are enabled during an I/O transfer. The memory
read and memory write control lines are enabled during a
memory transfer. This configuration isolates all I/O interface
addresses from the addresses assigned to memory an is
referred to as the isolated I/O or I/O mapped I/O method for
assigning addresses in common bus. The CPU I/O
Memory signals and
Address
address spaces are shown below.
Address Space Address Space
Data
CPU
Memory R/W’
I/O R/W’
 Common Address Data and Control
bus for Memory and I/O
In this case, computers use only one set of read and write
signals and do not distinguish between memory and I/O
addresses. This configuration is referred to as memory
mapped I/O. The processor treats an I/O interface register as
being part of the memory system. In other words, the
processor uses a portion of the memory address to represent
I/O interface. Computers with memory mapped I/O can use
memory type instructions to access I/O data. It allows the
computer to use the same instructions for either I/O
transfers or for memory transfers. The figure below depicted
Address
the CPU signals and address spaces Space mapped I/O.
in memory
division
Address I/O address
CPU Data

Memory R/W’ Memory address

Example of I/O interface unit

CS S1 S0
0 x x : No operation
1 0 0 : Port A register
1 0 1 : Port B register
2 1 0 : Control register
1 1 1 : Status register
 Synchronous Data Transfer
There are two types of data transfer depending on the mechanism
of timing the data they are Synchronous and Asynchronous data
transfers. In case of synchronous data transfer, the sending and
receiving units are enabled with same clock signal. The
synchronous transfer is possible between two units when each of
them knows the behavior of the other. The master performs a
sequence of actions for data transfer in a predetermined order;
each action is synchronized with the common clock. The master is
designed to supply the data at a time when the slave is definitely
ready for it. Usually, the master will introduce sufficient delay to
take into account the slow response of the slave, without any
request from the slave. The master does not except any
acknowledgement signal from the slave, when the data is sent by
the master to the slave.
Similarly, when a data from slave is read by the master,
neither the slave informs that a data has been placed on the data
bus nor the master acknowledges that a data has been read. Both
master and slave perform their own task of transferring data at
designated clock period. Since both devices know the behavior
(response time) of each other, no difficulty arises. Prior to
transferring data, the master must logically select the slave either
by sending slave’s address or sending “device select” signal to the
Synchronous read operation
Advantages of Synchronous Transfer :
1. The design procedure is easy. The master does not wait
for any
acknowledge signal from the slave though the
master waits for a
time equal to slave’s response time.
2. The slave does not generate acknowledge signal, though
it obeys the timing rules as per the protocol set by the
master or system designer.

Disadvantages of Synchronous Transfer :

1. If slow speed unit is connected to a common bus, it can
degrade
overall rate of transfer in the system.
2. If the slave operates at a slow speed, the master will be
idle for some
time during data transfer and vice versa.
 Asynchronous Transfer
There is no common clock between the master and slave in
asynchronous transfer. Each has its own private clock for
internal operations. This approach is widely used in most
computers. Asynchronous data transfer between two
independent units requires that control signals be transmitted
between the communicating units to indicate the time at which
data is being transmitted. One simple way is to use a strobe
signal supplied by one of the units to indicate the other unit
when the transfer has to occur.
Strobe Control Technique :
A single control line is used by the strobe control method of
asynchronous data transfer to time each transfer. The strobe
may be activated by either the source or the destination unit.
For source initiated strobe signal the source takes care
of proper timing delay between the actual data signals and the
strobe signal. The source places the data first, and after some
delay, generates the strobe to inform about the data on the
data bus. Before removing the data, source removes the strobe
and after some delay it removes the data. By these two leading
and trailing end delays, the system ensure the reliable data
Source – initiated strobe for data
transfer
Data bus
Destinatio
Source
n
Unit Strobe
Unit

Block diagram

Data bus Valid data

Strobe

Timing diagram
 Destination initiated strobe
Similarly, the destination can initiate data transfer by
sending strobe signal to the source unit. In response, the
source unit places data on the data bus. After receiving data,
the destination unit removes the strobe signal. Only after
sensing the removal of strobe signal, the source removes the
data from the data bus. The diagram of the destination
initiated strobe technique is shown in the next slide.

Disadvantages of strobe control technique :

The disadvantage of the strobe method is that the source
unit that initiates the transfer cannot know whether the
destination unit has actually received the data item that was
placed in the bus.
Similarly, a destination unit that initiates the transfer
cannot know whether the source unit has actually placed
the data on the bus.
Destination initiated strobe for data
transfer
Data bus
Destinatio
Source
n
Unit Strobe
Unit

Block diagram

Strobe

Data bus Valid data

Timing diagram
 Handshaking Technique
To overcome the problem of strobe technique, another method
commonly used is to accompany each data item being transferred
with a control signal that indicates the presence of data in the
bus. The unit receiving the data item responds with another
control signal to acknowledge receipt of the data. This type of
agreement between two independent units is referred to as
handshaking mode of transfer.
For source initiated transfer, the source first places the
data on the data bus and after some delay issues the “data valid”
signal. On sensing the data valid signal the destination receives
the data and then issues the acknowledgement signal “data
accepted” to indicate the acceptance of data. On sensing the data
accepted signal the source removes data and data valid signal. On
sensing removal of data valid signal, the destination removes the
data accepted signal.
For Destination initiated handshaking technique the
destination first sends the “data request” signal. On sensing this
signal, the source places data and also issue the “data valid”
signal. On sensing data valid signal, the destination acquires data
and then removes the data request signal. On sensing this, the
source removes both the data and data valid signal. The two type
of initiations are shown diagrammatically in the next two slides.
Source – initiated transfer using
handshaking
Data bus
Destinatio
Source
Data valid n
Unit
Unit
Data accepted

Block diagram

Data bus Valid data

Data valid

Data accepted

Timing diagram
Destination – initiated handshaking
Data request
Destinatio
Source Data bus
n
Unit
Unit
Data valid

Block diagram

Data request

Data Valid data

Data valid

Timing diagram
Advantage of handshaking technique :
The advantage of handshaking scheme is that it provides a
high degree of flexibility and reliability because the
successful completion of a data transfer relies on active
participation by both units.

Disadvantages of handshaking technique :

1. A slow speed destination unit can hold up the bus
whenever it gets a chance to communicate.
2. If one of the two communicating devices is faulty, the
initiated data transfer cannot be completed.

Examples of asynchronous transfer :

1. The centronics interface follows handshaking scheme.
2. Most microprocessors such as Motorola 88010 and Intel
80286 follow this bus transfer mechanism.
Thank you