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Lecture 4.1 - The Processor

Chapter 4

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Divyansh Maurya
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7 views

Lecture 4.1 - The Processor

Chapter 4

Uploaded by

Divyansh Maurya
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Chapter 4

The
Processor
Our Single-Core
Computer
Processor Memory
Enable? Input
Read/Write
Control

Cac he Program
Datapath Memory (including
Address cache) organized
PC around blocks,
Bytes which are typically
Write multiple words
Registers Data

Arithmetic & Logic Unit Data


(ALU) Read Output

Data
Processor organized
around words and bytes
Processor-Memory Interface I/O-Memory Interfaces
The
Processor
• Processor (CPU): The active part of the
computer that does all the work (data
manipulation and decision-making)

• Datapath: Portion of the processor that


contains hardware necessary to perform
operations required by the processor

• Control: Portion of the processor (also in


hardware) that tells the datapath what needs
Single-Cycle
Implementation
Instructions
Memory ld Sd
Reference
Arithmetic/ add sub and or
Logical
Control Transfer beq
Instruction
Execution
 PC  instruction memory, fetch
instruction
 Register numbers  register file, read
registers
 Depending on instruction class
 Use ALU to calculate
 Arithmetic result
 Memory address for load/store
 Branch comparison
 Access data memory for load/store
 PC  target address or PC + 4
Stages of the Datapath :
Overview
• Problem: A single block that executes an
instruction (performs all necessary operations
beginning with fetching the instruction) would
be too bulky and inefficient

• Solution: Break up the process of “executing an


instruction” into stages, and then connect the
stages to create the whole datapath
– smaller stages are easier to design
– easy to optimize (change) one stage without
touching the others (modularity)
Five Stages of the
Datapath
 Stage 1: Instruction Fetch (IF)

 Stage 2: Instruction Decode (ID)


 Stage3: Execute (EX) – ALU (Arithmetic-
Logic Unit)
 Stage 4: Memory Access (MEM)
 Stage 5: Write Back to Register (WB)
Overview of
Implementation

First Two Steps:
 Send the program counter (PC) to the memory
that contains the code and fetch the instruction
from that memory

 Read one or two registers, using fields of the


instruction to select the registers to read. For the load
word instruction, we need to read only one register, but
most other instructions require reading two registers.
Instruction
Fetching
 The CPU is always in an infinite loop,
fetching instructions from memory
and executing them.
 The PC register holds the address of
the current instruction
Instruction
Fetch

Increment
by 4 for
next
64-bit
instruction
regist
er
CPU
Overview
 The value written into the PC can come
from one of two adders
 Then, the data written into the
register file can come from either the
ALU or the data memory
 Second input to the ALU can come from
a register or the immediate field of the
instruction
 Add a multiplexor to select from
several inputs based on the setting of
its control lines to send to the output.
 Also called data selector
 Control lines are set based on
information taken from the instructions
being executed
Building a
Datapath
 Datapath
 Elementsthat process data and
addresses in the CPU
 Registers, ALUs, mux’s, memories, …

 We will build a RISC-V datapath


incrementally
 Refining the overview design
Composing the
Elements
First-cut data path does an instruction in
one clock cycle
 Each datapath element can only do one
function at a time
 Hence, we need separate instruction and
data memories
 Use multiplexers where alternate data
sources are used for different
instructions
Registers and an
ALU
 Our register file stores 32-bit
values
 Each register specifier is 5 bits long
 You can read from 2 registers at a
time
 RegWrite is 1 if a register should
be written
 ALU with 5 operations, selected by a 3-bit control
signal ALUOp
ALU
Control
 ALU used for
 Load/Store: F = add
 Branch: F = subtract
 R-type: F depends on
opcode

ALU control Function


0000 AND
0001 OR
0010 add
0110 subtract
ALU
Control
 Assume 2-bit ALUOp derived from
opcode
 Combinational logic derives ALU
control ALU
opcode ALUOp Operation Opcode field ALU function control
ld 00 load register XXXXXXXXXXX add 0010
sd 00 store register XXXXXXXXXXX add 0010
beq 01 branch on equal XXXXXXXXXXX subtract 0110

R-type 10 add 100000 add 0010


subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001
Memori
es
 To fetch instructions and
read & write words, we
need these memories to
be 32-bits wide
 Buses are represented
by dark lines here

 Blue lines represent control


signals. MemRead and
MemWrite should be set
to 1 if the data memory is
to be read or written
The Main Control
Unit
R-Format
Instructions
 Read two register operands

 Perform arithmetic/logical
operation
 Write register result
R-Type
Instruction
Load/Store
Instructions
 Read register operands

 Calculate address using 12-bit


offset
 Use ALU, but sign-extend offset
 Load: Read memory and update
register
 Store: Write register value to
memory
Load
Instruction
Branch
Instructions
 Read register operands

 Compare operands
 Use ALU, subtract and check Zero
output
 Calculate target
address
 Sign-extend
displacement
 Shift left 1 place
(halfword
displacement)
 Add to PC value
Branch
Instructions
Just
re-
routes
wire
s

Sign-bit
wire
replicate
d
BEQ
Instruction
Contr
ol
Multiplex
ers
 Can’t just
join wires
together

Use
multiplexer
s

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