Chapter 2.

Machine Instructions
and Programs
Objectives
 Machine instructions and program execution, including branching and
subroutine call and return operations.
 Number representation and addition/subtraction in the 2’s-complement
system.
 Addressing methods for accessing register and memory operands.
 Assembly language for representing machine instructions, data, and
programs.
 Program-controlled Input/Output operations.
Number, Arithmetic Operations,
and Characters
 Computers operate on information represented by two
valued electrical signals labeled as 0 and 1
 The amount information represented by such signal is
defined as the bit of information
 Bit stands for binary digit.
 A number in a computer system is represented by a string
of bits, called as binary number
 A text character is also represented by a string of bits,
called as Character code
Number representation
Signed Integer
3 major representations:
Sign and magnitude
One’s complement
Two’s complement
 Assumptions:

4-bit machine word

16 different values can be represented
Roughly half are positive, half are negative
Sign and Magnitude Representation
-7 +0
-6 1111 0000 +1
1110 0001
-5 +2 +
1101 0010
-4 1100 0011 +3 0 100 = + 4

-3 1011 0100 +4 1 100 = - 4

1010 0101
-2 +5 -
1001 0110
-1 1000 0111 +6
-0 +7
High order bit is sign: 0 = positive (or zero), 1 = negative
Three low order bits is the magnitude: 0 (000) thru 7 (111)
Number range for n bits = -(2n-1 -1) to +(2n-1 -1)
Two representations for 0
One’s Complement Representation
-0 +0
-1 1111 0000 +1
1110 0001
-2 +2 +
1101 0010
-3 1100 0011 +3 0 100 = + 4

-4 1011 0100 +4 1 011 = - 4

1010 0101
-5 +5 -
1001 0110
-6 1000 0111 +6
-7 +7
 1’s complement is obtained by changing 0 to 1 and 1 to 0 in a number
 Number range for n bits = -(2n-1 -1) to +(2n-1 -1)

 Subtraction implemented by addition & 1's complement

 Still two representations of 0! This causes some problems

 Some complexities in addition

Two’s Complement Representation
-1 +0
-2 1111 0000 +1
1110 0001
-3 +2 +
1101 0010
like 1's comp
except shifted -4 1100 0011 +3 0 100 = + 4
one position
clockwise -5 1011 0100 +4 1 100 = - 4
1010 0101
-6 +5 -
1001 0110
-7 1000 0111 +6
-8 +7
 2’ s complement is obtained by adding 1 to 1’s complement

 2’s complement = 1’s complement +1

 Only one representation for 0

 Number range for n bits = -(2n-1 ) to +(2n-1 -1)

 One more negative number than positive number

Binary, Signed-Integer Representations
B V alues represented
Page 28
Sign and
b3 b2b1b0 magnitude 1' s complement 2' s complement

0 1 1 1 +7 +7 + 7
0 1 1 0 +6 +6 + 6
0 1 0 1 +5 +5 + 5
0 1 0 0 +4 +4 + 4
0 0 1 1 +3 +3 + 3
0 0 1 0 +2 +2 + 2
0 0 0 1 +1 +1 + 1
0 0 0 0 +0 +0 + 0
1 0 0 0 - 0 -7 - 8
1 0 0 1 - 1 -6 - 7
1 0 1 0 - 2 -5 - 6
1 0 1 1 - 3 -4 - 5
1 1 0 0 - 4 -3 - 4
1 1 0 1 - 5 -2 - 3
1 1 1 0 - 6 - 1 - 2
1 1 1 1 - 7 -0 - 1

Figure 2.1. Binary, signed-integer representations.

Addition and Subtraction – 2’s Complement
4 0100 -4 1100
+3 0011 + (-3) 1101
If carry-in to the high
order bit =
carry-out then ignore
carry

if carry-in differs from 4 0100 -4 1100

carry-out then overflow
-3 1101 +3 0011

Simpler addition scheme makes twos complement the most common

choice for integer number systems within digital systems
The rules for addition and subtraction of n-bit signed
numbers using the 2’s-complement representation

 To add two numbers, add their n-bit representations, ignoring the

carry-out bit from the most significant bit (MSB) position. The sum
will be the algebraically correct value in2’s-complement
representation if the actual result is in the range −2 n−1 through
+2 n−1− 1.
 To subtract two numbers X and Y , that is, to perform X − Y , form

the 2’s-complementof Y , then add it to X using the add rule.

Again, the result will be the algebraically correct value in 2’s-
complement representation if the actual result is in the range
−2 n−1through +2 n−1− 1
2’s-Complement Add and Subtract
Operations
(a) 0010 ( + 2) (b) 0100 ( + 4)
+ 0011 ( + 3) + 1010 (- 6)
Page 31 (- 2)
0101 ( + 5) 1110
(c) 1011 (- 5) (d) 0111 ( + 7)
+ 1110 (- 2) + 1101 ( - 3)
1001 (- 7) 0100 ( + 4)
(e) 1101 (- 3) 1101
- 1001 (- 7) + 0111
0100 ( + 4)
(f) 0010 ( + 2) 0010
- 0100 ( + 4) + 1100
1110 ( - 2)
(g) 0110 ( + 6) 0110
- 0011 ( + 3) + 1101
0011 ( + 3)
(h) 1001 ( - 7) 1001
- 1011 (- 5) + 0101
1110 ( - 2)
(i) 1001 (- 7) 1001
- 0001 ( + 1) + 1111
1000 ( - 8)
(j) 0010 ( + 2) 0010
- 1101 ( - 3) + 0011
0101 ( + 5)

Figure 2.4. 2's-complement Add and Subtract operations.

Overflow condition

 Ifcarry-in to the high order bit (MSB) = carry-out of higher

order bit (MSB)
 then no overflow ignore the carry

 Ifcarry-in to the high order bit (MSB) != carry-out of higher

order bit (MSB)
 then overflow condition , result is erroneous
Overflow - Add two positive numbers to get a negative number
or two negative numbers to get a positive number

-1 +0 -1 +0
-2 1111 0000 +1 -2 1111 0000 +1
1110 0001 1110 0001
-3 +2 -3
1101 1101 +2
0010 0010
-4 -4
1100 0011 +3 1100 0011 +3
-5 1011 -5 1011
0100 +4 0100 +4
1010 1010
-6 0101 -6 0101
1001
+5 +5
0110 1001
0110
-7 1000 0111 +6 -7 1000 +6
0111
-8 +7 -8 +7

5 + 3 = -8 -7 - 2 = +7
Overflow Conditions
1000
5 0101 -7 1001
3 0011 -2 1100

Overflow Overflow
0000 1111
5 0101 -3 1101
2 0010 -5 1011

No overflow No overflow
Overflow when carry-in to the high-order bit does not equal carry out
Sign Extension
 Task:
 Given w-bit signed integer x
 Convert it to w+k-bit integer with same value

 Rule:
 Make k copies of sign bit:

 X= x
w–1 ,…, xw–1 , xw–1 , xw–2 ,…, x0
w
X • • •
k copies of MSB

• • •

X • • • • • •
k w
Sign Extension Example

short int x = 15213;

int ix = (int) x;
short int y = -15213;
int iy = (int) y;

Decimal Hex Binary

x 15213 3B 6D 00111011 01101101
ix 15213 00 00 C4 92 00000000 00000000 00111011 01101101
y -15213 C4 93 11000100 10010011
iy -15213 FF FF C4 93 11111111 11111111 11000100 10010011
Memory Locations, Addresses,
and Operations
Memory Location, Addresses, and
Operation
n bits
first word
 Memory consists of many
second word
millions of storage cells,
each of which can store 1
bit. •
•
 Data is usually accessed •
in n-bit groups called as i th word
word. n is called word
length.
•
•
•
last word

Figure 2.5. Memory words.

Memory Location, Addresses, and
Operation
 32-bit word length example
32 bits

b 31 b 30 b1 b0

•
•
•
Sign bit: b 31= 0 for positive numbers
b 31= 1 for negative numbers

(a) A signed integer

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

character character character character

(b) Four characters

Memory Location, Addresses, and
Operation
 To retrieve information from memory, either for one word or one byte
(8-bit), addresses for each location are needed.
 A k-bit address memory has 2k memory locations, namely 0 – 2k-1,
called memory space.
 24-bit memory: 224 = 16,777,216 = 16M (1M=220)
 32-bit memory: 232 = 4G (1G=230)
 1K(kilo)=210
 1T(tera)=240
Memory Location, Addresses, and
Operation
BYTE ADDRESSABILITY
 It is impractical to assign distinct addresses to individual bit

locations in the memory.

 The most practical assignment is to have successive

addresses refer to successive byte locations in the memory –

i.e. byte-addressable memory.
 Byte locations have addresses 0, 1, 2, … If word length is 32

bits, they successive words are located at addresses 0, 4, 8,

…
Big-Endian and Little-Endian
Assignments
Big-Endian: lower byte addresses are used for the most significant bytes of the word
Little-Endian: opposite ordering. lower byte addresses are used for the less significant
bytes of the word
Word
address Byte address Byte address

0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

• •
• •
• •

k k k k k k k k k k
2 -4 2 -4 2 -3 2- 2 2 - 1 2 - 4 2- 1 2 - 2 2 -3 2 -4

(a) Big-endian assignment (b) Little-endian assignment

Figure 2.7. Byte and word addressing.

 EX: If num=12345678

Big Endian Little Endian

0
12 0 78
1 34 56
1
2 56 34
2
3 78 12
3
Memory Location, Addresses, and
Operation
 Address ordering of bytes
 Word alignment
 Words are said to be aligned in memory if they begin at a byte addr.
that is a multiple of the num of bytes in a word.
 16-bit word: word addresses: 0, 2, 4,….
 32-bit word: word addresses: 0, 4, 8,….
 64-bit word: word addresses: 0, 8,16,….
 Access numbers, characters, and character strings
Memory Operation
 Load (or Read or Fetch)
 Copy the content. The memory content doesn’t change.
 Address – Load
 Registers can be used
 Store (or Write)
 Overwrite the content in memory
 Address and Data – Store
 Registers can be used
Instruction and Instruction
Sequencing
“Must-Perform” Operations
 Data transfers between the memory and the processor
registers
 Arithmetic and logic operations on data
 Program sequencing and control
 I/O transfers
Register Transfer Notation
 Identify
a location by a symbolic name standing for its
hardware binary address (LOC, R0,…)
 Contents of a location are denoted by placing square

brackets around the name of the location (R1←[LOC], R3

←[R1]+[R2])
 Register Transfer Notation (RTN)
Assembly Language Notation
 Represent machine instructions and programs.
 Move LOC, R1 = R1←[LOC]
 Add R1, R2, R3 = R3 ←[R1]+[R2]
CPU Organization
 Single Accumulator
 Result usually goes to the Accumulator
 Accumulator has to be saved to memory quite
often
 General Register
 Registers hold operands thus reduce memory
traffic
 Register bookkeeping
 Stack
 Operands and result are always in the stack
 Instruction Formats
 Three-Address Instructions
 ADD A,B,C C←[ A] +[ B]
 Operation source1, source2,destination
 Two-Address Instructions
 ADD A, B B ← [A] +[B]
 Operation source, destination
 One-Address Instructions
 ADD A AC ← AC + [A]
 LOAD A AC←[A]
 STORE A [A]←AC
Zero-Address Instructions
 INC AC ← AC+1

Opcode Operand(s) or Address(es)

 C←[ A] +[ B]
Three-Address Instructions
 ADD A,B,C

Two-Address Instructions
• ADD A,B
• MOVE B,C

One-Address Instructions
• LOAD A
• ADD B
• STORE C
Using Registers
 Registers are faster
 Shorter instructions
 The number of registers is smaller (e.g. 32 registers need 5 bits)
 Minimize the frequency with which data is moved back and
forth between the memory and processor registers.
 Let Ri represents a general purpose register,
 LOAD A,Ri
 STORE Ri,A
 ADD A,Ri
 Only one memory address is specified in instruction, still may

not fit into one word

Instuctions may have only registers
 ADD Ri,Rj
 ADD Ri, Rj, Rk

Since only registers in instruction , it fits into one word

 MOVE A,Ri is same as LOAD A,Ri
 MOVE Ri,A is same as STORE Ri,A

EX:C=A+B ,if arithmetic operations are allowed on registers

MOVE A,Ri
MOVE B,Rj
ADD Ri,Rj
Move Rj,C
Instruction Formats
Example: Evaluate X= (A+B)  (C+D)
 Three-Address

1. ADD A, B,E ; E ← [A] +

[B]
2. ADD C, D,F ; F ← [C] +
[D]
3. MUL E, F,X ; X ← [E]*[F]
Instruction Formats
Example: Evaluate X= (A+B)  (C+D)
 Two-Address

1. ADD A,B ; B←[A] + [B]

2. ADD C, D ; D ← [C] +
[D]
3. MUL B,D ; D ← [B] 
[D]
4. MOV D,X ; X ← [D]
Instruction Formats
Example: Evaluate X=(A+B)  (C+D)
 One-Address

1. LOAD A ; AC ← [A]
2. ADD B ; AC ← AC +
[B]
3. STORE T ; [T] ← AC
4. LOAD C ; AC ← [C]
5. ADD D ; AC ← AC +
[D]
6. MUL T ; AC ← AC 
[T]
7. STORE X ; [X] ← AC
Instruction Execution and Straight-Line
Sequencing
Address Contents

i
Assumptions:
Begin execution here Move A,R0
i+4
3-instruction
program
- One memory operand
Add B,R0
segment per instruction
i+8 Move R0,C
- 32-bit word length
- Memory is byte
addressable
A - Full memory address
can be directly specified
in a single-word instruction
B Data for
the program
Two-phase procedure
-Instruction fetch
-Instruction execute
C
Page 43

Figure 2.8. A program for C ¬ [A] + [B].

 i Move NUM1,R0
i+4 Add NUM2,R0

Branching i+8 Add NUM3,R0

•
•
•
i + 4n - 4 Add NUMn,R0
i + 4n Move R0,SUM

•
•
•
SUM
NUM1
NUM2

•
•
•
NUMn

Figure 2.9. A straight-line program for adding n numbers.

 Move N,R1
Clear R0

Branching LOOP
Determine address of
"Next" number and add
Program "Next" number to R0
loop
Decrement R1
Branch>0 LOOP
Branch target
Move R0,SUM

Conditional branch

•
•
•
SUM
N n
NUM1

Figure 2.10. Using a loop to add n numbers. NUM2

•
•
•
NUMn
Condition Codes
 Condition code flags
 Condition code register / status register
 N (negative)
 Z (zero)
 V (overflow)
 C (carry)
 Different instructions affect different flags
Conditional Branch Instructions
 Example: A: 11110000
 A: 1 1 1 1 0 0 0 0 +(−B): 1 1 1 0 1 1 0 0
 B: 0 0 0 1 0 1 0 0 11011100

C=1 Z=0
S=1
V=0
Status Bits

Cn-1
A B

Cn ALU
F
V Z S C
Fn-1

Zero Check