INSTITUTE UIE

DEPARTMENT ACADEMIC UNIT-2

Bachelor of Engineering (Computer Science & Engineering)
Subject Name Fundamental of Electrical & Digital Electronics
Subject Code 24ECH-101
Prepared By
Dr. Rachit Manchanda
Unit-2 Chapter-1
Combinational Circuits
Lecture No. 2.1.7
DISCOVER . LEARN . EMPOWER
 Lecture
Objectives
S. No. Objectives
To make student aware about the derivation of logic for the design of Encoder, decoder &
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Magnitude Comparator.

2 To aware about implementation of Encoder, decoder & Magnitude Comparator circuit.

To learn about design of different design of Encoder, decoder & Magnitude Comparator.
3
.

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 Course Objectives
1. The course is designed to make the students develop a strong foundation in basic electrical & digital electronics
concepts.
2. It will make the students competent to gain the skills and knowledge required to design and implement combinational
and sequential logic circuits for various applications.
3. It will enhance the skill level of the students in building, testing, and troubleshooting digital circuits to enhance their
practical skills and problem-solving abilities and shall make them preferred choice for getting employment in industry
and research labs.
4. It will give thorough knowledge of the discipline to enable students to disseminate knowledge in pursuing excellence in
academic areas.

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 Course
Outcomes
CO
Numbe Title Level
r

To identify the different types of electrical elements, combinational &

CO1 Remember
sequential circuits and to state the different methods for describing them.

To understand the basic principles of electrical circuits, Binary arithmetic’s,

CO2 Boolean algebra and to understand the different methods for designing and Understand
optimizing the digital circuits.

To examine the various digital logic designs, combinational, sequential &

CO3 Apply
electrical circuits and to solve various problems related to it.

To analyse the various digital logic designs, combinational sequential &

CO4 electrical circuits and to outline the characteristics of different configurations Analyze
associated to them.

CO5 To assess the different applications of Counters and shift registers. Evaluate Figure showing same application
but different technology

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 ENCODER
• An Encoder is a combinational logic circuit.
• It performs the inverse operation of Decoder.
• The opposite process of decoding is known as Encoding.
• An Encoder converts an active input signal into a coded output signal.
• Block diagram of Encoder is shown in Fig.1.1. It has ‘M’ inputs and ‘N’ outputs.
• An Encoder has ‘M’ input lines, only one of which is activated at a given time, and produces an N-bit
output code, depending on which input is activated.

A0 A1 B0
‘M’ Inputs

‘N’ Outputs
A2 B1
B2

-------
-------

Encoder

AM-1 BN-1

Fig. 6: - ENCODER DIAGRAM

• Encoders are used to translate the rotary or linear motion into a digital signal.
• The difference between Decoder and Encoder is that Decoder has Binary Code as an input while
Encoder has Binary Code as an output.
• Encoder is an Electronics device that converts the analog signal to digital signal such as BCD Code.

Types of Encoders
i. Priority Encoder
ii. Decimal to BCD Encoder
iii. Octal to Binary Encoder
iv. Hexadecimal to Binary Encoder
ENCODER

M=4 M=22
M=2N
‘M’ is the input and ‘N’
is the output

A0
B0
A1
B1
A2 Encoder 4 Decoder 2
B2
A3 x2 x4
B3

Fig. 7: ENCODER DIAGRAM

ENCODER
M=4 M=22
M=2N
‘M’ is the input and ‘N’
is the output

00
A0
01
A1
A2
10 Encoder 4 Decoder 2
11 x2 x4
A3

Fig. 8 ENCODER DIAGRAM

ENCODER
M=4 M=22
M=2N
‘M’ is the input and ‘N’
is the output

00
A0
01 1
A1
A2
10 Encoder 4 0
Decoder 2
A3
11 x2 x4

Fig. 9: ENCODER DIAGRAM

ENCODER
M=4 M=22
M=2N
‘M’ is the input and ‘N’
is the output

00
A0
01 1
A1
A2
10 Encoder 4 0
Decoder 2
10
A3
11 x2 x4

Fig. 10: ENCODER DIAGRAM

 PRIORITY ENCODER
• As the name indicates, the priority is given to inputs line.
• If two or more input lines are high at the same time i.e 1 at the same time, then the input line with high
priority shall be considered.
• Block diagram and Truth table of Priority Encoder are shown in fig. 1.6.
Highest Priority
Input TRUTH TABLE:

D3 INPUTS OUTPUTS V
Y1
D2 D3 D2 D1 D0 Y1 Y0
Priority 0 0 0 0 x x 0
D1 Encoder
0 0 0 1 0 0 1
Y0
D0 0 0 1 x 0 1 1
0 1 x x 1 0 1
Lowest Priority Output 1 x x x 1 1 1
Input
Block Diagram of Priority Encoder Fig. 1 1 : ENCODER DIAGRAM
 • There are four inputs D0, D1,D2, D3 and two outputs Y1 and Y2.
• D3 has highest priority and D0 is at lowest priority.
• If D3=1 irrespective of other inputs then output Y1Y0=11.
• D3 is at highest priority so other inputs are considered as don’t care.

K-map for Y1 and Y0

D 1D 0 D 1D 0
D 3D 2 00 01 11 10 D 3D 2 00 01 11 10

00 X 0 0 0 00 X 0 1 1

01 1 1 1 1 01 0 0 0 0

11 1 1 1 1 11 1 1 1 1

10 1 1 1 1 10 1 1 1 1

Y1  D 2  D 3
Y 0  D 3 D D 2 1

Fig. 12 : ENCODER DIAGRAM

LOGIC DIAGRAM OF PRIORITY ENCODER:
Y1  D 2  D 3
Y0  D2 D1 + D3

D3 D2 D1 D0

Y1

Y0

Fig. 13 : ENCODER DIAGRAM

 DECIMAL TO BCD ENCODER:
• It has ten inputs corresponding to ten decimal digits (from 0 to 9) and four outputs (A,B,C,D) representing the
BCD.

0
A
1
2 B
-------- -

ENCODER

9 D
INPUTS OUTPUTS
Fig. 14 : ENCODER DIAGRAM
 Truth Table
INPUTS BCD OUTPUTS
0 1 2 3 4 5 6 7 8 9 A B C D
1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 0 0 0 1 0 0
0 0 0 0 0 1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 0 0 0 0 1 1 0
0 0 0 0 0 0 0 1 0 0 0 1 1 1
0 0 0 0 0 0 0 0 1 0 1 0 0 0
0 0 0 0 0 0 0 0 0 1 1 0 0 1

Fig. 15 : ENCODER DIAGRAM

• From Truth Table it is clear that the output A is HIGH when input is 8 OR 9 is HIGH
Therefore A=8+9
• The output B is HIGH when 4 OR 5 OR 6 OR 7 is HIGH Therefore B=4+5+6+7
• The output C is HIGH when 2 OR 3 OR 6 OR 7 is HIGH
Therefore C=2+3+6+7
• Similarly D=1+3+5+7+9
Logic Diagram is shown in fig. 1.11
+5V DECIMAL TO BCD ENCODER
0
1
2
3
4
5
6
7
8
9

A B C D
Fig. 16: ENCODER DIAGRAM
 OCTAL TO BINARY ENCODER
• Block Diagram of Octal to Binary Encoder is shown below.
• It has eight inputs and three outputs.
• Only one input has one value at any given time.
• Each input corresponds to each octal digit and output generates
corresponding Binary Code.

D0
D1 X
D2
D3 ENCODER Y
D4
D5
D6 Z
D7
INPUT OUTPUT
Fig. 17: ENCODER DIAGRAM
TRUTH TABLE
INPUT OUTPUT

D0 D1 D2 D3 D4 D5 D6 D7 X Y Z

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1

Fig. 18 : ENCODER DIAGRAM

 X  D 4  D5  D6  D7
Y  D 2  D3  D6  D7
Z  D1  D 3  D 5  D 7
LOGIC DIAGRAM
D0 D1 D2 DD34 D5 D6 D7

X  D4  D5  D6  D7

Y  D2  D3  D6  D7

Z  D1  D 3  D 5  D 7

Fig. 19: ENCODER

DIAGRAM
Decoder
Design of 2-to-4 Decoder
Questions:
1. Implement the following function using 3:8 decoder.
• Y0(A,B,C)=(0,1,2,4)
• Y1(A,B,C)=(1,3,5,7)
• Y2(A,B,C)=(4,5,6,7)

2. Design a full adder using 3 to 8 line decoder.

 Magnitude Comparator
It is a combinational logic circuit.

Magnitude Comparator is used to compare the value of two binary digits.

There are two types of digital comparator (i) Identity Comparator (ii) Magnitude Comparator.

IDENTITY COMPARATOR : This comparator has only one output terminal for when A=B, either
A=B=1 (High) or A=B=0 (Low) .
MAGNITUDE COMPARATOR : This Comparator has three output terminals namely A>B, A=B, A<B.
Depending on the result of comparison, one of these output will be high.

In comparator corresponding to n-bit we have 2n number of Inputs .

.
Figure 2 Block Diagram of n-bit Magnitude
Comparator
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 Classification of Comparators
 1-bit Comparator
 2-bit Comparator

Fig 3 1-bit Comparator Fig 4: 2-bit Comparator

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 1-Bit Magnitude Comparator
•This magnitude comparator has two inputs A and B and three outputs A<B, A=B and
A>B.

•This magnitude comparator compares the two numbers of single bits.

Fig 5 Truth Table of 1-Bit Comparator

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1-Bit Magnitude Comparator

Fig 6 K-Maps for all three

outputs

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• A>B: AB‘ A<B: A'B A=B: A'B' + AB
From the above expressions we can derive the following formula:

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1-Bit Magnitude Comparator

Fig 7 Realization of 1-bit

Comparator

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1-Bit Magnitude Comparator

Fig 8: Realization of by Using AND, EX-NOR

gates

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 2-Bit Magnitude Comparator
A comparator which is used to compare two binary numbers each of two bits is called a 2-bit
magnitude comparator.
It has four inputs and three outputs.
Inputs are A0,A1,B0 and B1 and Outputs are Y1,Y2 and Y3.

Fig 9: Block diagram of 2-bit

Comparator

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2-Bit Magnitude Comparator

Fig 10: Truth table of 2-bit

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Comparator
2-Bit Magnitude Comparator

Fig 11: K-Maps of 2-bit Comparator

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2-Bit Magnitude Comparator

Fig 12: K -Map of 2-bit Comparator

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2-Bit Magnitude Comparator

Fig 13 Realization of 2-bit Comparator

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 REFERENCES
• https://
www.google.com/url?sa=i&url=https%3A%2F%2Ffanyv88.com%3A443%2Fhttps%2Fwww.indiamart.com%2Fproddetail%2Fmultiplexer-and-demultiplexer-tr
ainer-9336916362.html&psig=AOvVaw3rvmgb8TYvQK2MTxMP2mes&ust=1595882004114000&source=images&cd=vfe&
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• https://
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AAAABAJ

• https://
www.google.com/search?q=combinational+circuits+in+digital+electronics&source=lnms&tbm=i
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• https://
www.google.com/url?sa=i&url=https%3A%2F%2Ffanyv88.com%3A443%2Fhttps%2Fsimple.wikipedia.org%2Fwiki%2FMultiplexer&ps37
 REFERENCES
• https://
www.google.com/url?sa=i&url=https%3A%2F%2Ffanyv88.com%3A443%2Fhttp%2Fwww.vlsi-expert.com%2F2013%2F12%2Fdigital-b
asic-15-multiplexer-mux.html&psig=AOvVaw3xN1zjAPc331kKANSJ_As5&ust=1595886452950000
&source=images&cd=vfe&ved=0CAIQjRxqFwoTCOCG_Ljy6-oCFQAAAAAdAAAAABAD

• Mano,Morris, Digital Design, Prentice Hall of India.

• Fletcher, An Engg. Approach to digital design, Prentice Hall of India.

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THANK YOU